DRAM technology compatible processor/memory chips
First Claim
1. An address decoder for a memory device, the address decoder comprising:
- a number of address lines;
a number of output lines;
wherein the address lines, and the output lines form an array;
a number of non-volatile memory cells that are disposed at intersections of output lines and address lines, wherein at least one non-volatile memory cell includes a metal oxide semiconductor field effect transistor (MOSFET), a stacked capacitor formed according to a dynamic random access memory (DRAM) process, the capacitor providing a coupling ratio greater than 1.0, and an electrical contact that couples the stacked capacitor to a gate of the MOSFET; and
wherein the non-volatile memory cells are selectively programmed such that the non-volatile memory cells implement a logic function that selects an output line responsive to an address provided to the address lines.
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Accused Products
Abstract
The present invention includes an address decoder for a memory device. The address decoder includes a number of address lines and a number of output lines. The address lines, and the output lines form an array. A number of non-volatile memory cells are disposed at intersections of output lines and address lines. Each non-volatile memory cell includes a metal oxide semiconductor field effect transistor (MOSFET), a stacked capacitor formed according to a dynamic random access memory (DRAM) process, and an electrical contact that couples the stacked capacitor to a gate of the MOSFET. The non-volatile memory cells are selectively programmed such that the non-volatile memory cells implement a logic function that selects an output line responsive to an address provided to the address lines.
Methods, integrated circuits, and electronic systems are similarly provided and included within the scope of the present invention.
53 Citations
63 Claims
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1. An address decoder for a memory device, the address decoder comprising:
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a number of address lines;
a number of output lines;
wherein the address lines, and the output lines form an array;
a number of non-volatile memory cells that are disposed at intersections of output lines and address lines, wherein at least one non-volatile memory cell includes a metal oxide semiconductor field effect transistor (MOSFET), a stacked capacitor formed according to a dynamic random access memory (DRAM) process, the capacitor providing a coupling ratio greater than 1.0, and an electrical contact that couples the stacked capacitor to a gate of the MOSFET; and
wherein the non-volatile memory cells are selectively programmed such that the non-volatile memory cells implement a logic function that selects an output line responsive to an address provided to the address lines. - View Dependent Claims (2, 3, 4, 5)
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6. An address decoder for a memory device, the address decoder comprising:
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a number of address lines;
a number of output lines;
wherein the address lines, and the output lines form an array;
a number of non-volatile memory cells that are disposed at intersections of output lines and address lines, wherein at least one non-volatile memory cell includes a metal oxide semiconductor field effect transistor (MOSFET), a stacked capacitor formed according to a dynamic random access memory (DRAM) process, the capacitor providing a coupling ratio greater than 1.0, and an electrical contact that couples the stacked capacitor to a gate of the MOSFET;
wherein the non-volatile memory cells are selectively programmed such that the non-volatile memory cells implement a logic function that selects an output line responsive to an address provided to the address lines; and
wherein the decoder is operatively coupled to a dynamic random access memory (DRAM) device. - View Dependent Claims (7, 8, 9, 10, 11, 12)
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13. An address decoder for a memory device, the address decoder comprising:
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a number of address lines;
a number of output lines;
wherein the address lines, and the output lines form an array;
a number of non-volatile memory cells that are disposed at intersections of output lines and address lines, wherein at least one non-volatile memory cell includes a metal oxide semiconductor field effect transistor (MOSFET), a cup-shaped stacked capacitor formed according to a dynamic random access memory (DRAM) process, the capacitor providing a coupling ratio greater than 1.0, and an electrical contact that couples the stacked capacitor to a gate of the MOSFET; and
wherein the non-volatile memory cells are selectively programmed such that the non-volatile memory cells implement a logic function that selects an output line responsive to an address provided to the address lines. - View Dependent Claims (14, 15, 16, 17)
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18. An address decoder for a memory device, the address decoder comprising:
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a number of address lines;
a number of output lines;
wherein the address lines, and the output lines form an array;
a number of non-volatile memory cells that are disposed at intersections of output lines and address lines, wherein at least one non-volatile memory cell includes a metal oxide semiconductor field effect transistor (MOSFET) comprising a gate and a channel region separated by a gate oxide, a capacitor formed according to a dynamic random access memory (DRAM) process, the capacitor providing a coupling ratio greater than 1.0, and an electrical contact that couples the stacked capacitor to a gate of the MOSFET; and
wherein the non-volatile memory cells are selectively programmed such that the non-volatile memory cells implement a logic function that selects an output line responsive to an address provided to the address lines. - View Dependent Claims (19, 20, 21, 22, 23, 24)
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25. An address decoder for a memory device, the address comprising:
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a number of address lines;
a number of output lines;
wherein the address lines, and the output lines form an array;
a number of non-volatile memory cells that are disposed at intersections of output lines and address lines, wherein at least one non-volatile memory cell includes a metal oxide semiconductor field effect transistor (MOSFET) comprising a gate and a channel region separated by a gate oxide, a cup-shaped capacitor formed according to a dynamic random access memory (DRAM) process, the capacitor providing a coupling ratio greater than 1.0, and an electrical contact that couples the stacked capacitor to a gate of the MOSFET; and
wherein the non-volatile memory cells are selectively programmed such that the non-volatile memory cells implement a logic function that selects an output line responsive to an address provided to the address lines. - View Dependent Claims (26, 27, 28, 29, 30, 31)
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32. An address decoder for a memory device, the address decoder comprising:
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a number of address lines;
a number of output lines;
wherein the address lines, and the output lines form an array;
a number of non-volatile memory cells that are disposed at intersections of output lines and address lines, wherein at least one non-volatile memory cell includes a metal oxide semiconductor field effect transistor (MOSFET), a stacked capacitor formed according to a dynamic random access memory (DRAM) process, the capacitor providing a coupling ratio greater than 1.0, the capacitor including a bottom plate and a top plate separated by a capacitor dielectric, wherein an electrical contact couples the bottom plate of the capacitor to a gate of the MOSFET; and
wherein the non-volatile memory cells are selectively programmed such that the non-volatile memory cells implement a logic function that selects an output line responsive to an address provided to the address lines. - View Dependent Claims (33, 34, 35, 36, 37, 38)
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39. An address decoder for a memory device, the address decoder comprising:
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a number of address lines;
a number of output lines;
wherein the address lines, and the output lines form an array;
a number of non-volatile memory cells that are disposed at intersections of output lines and address lines, wherein at least one non-volatile memory cell includes a metal oxide semiconductor field effect transistor (MOSFET), a cup-shaped stacked capacitor formed according to a dynamic random access memory (DRAM) process, the capacitor providing a coupling ratio greater than 1.0, the capacitor including a bottom plate and a top plate separated by a capacitor dielectric, wherein an electrical contact couples the bottom plate of the capacitor to a gate of the MOSFET; and
wherein the non-volatile memory cells are selectively programmed such that the non-volatile memory cells implement a logic function that selects an output line responsive to an address provided to the address lines. - View Dependent Claims (40, 41, 42, 43, 44, 45)
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46. An address decoder for a memory device, the address decoder comprising:
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a number of address lines;
a number of output lines;
wherein the address lines, and the output lines form an array;
a number of non-volatile memory cells that are disposed at intersections of output lines and address lines, wherein at least one non-volatile memory cell includes a metal oxide semiconductor field effect transistor (MOSFET) comprising a gate and a channel region separated by a gate oxide, a cup-shaped stacked capacitor formed according to a dynamic random access memory (DRAM) process, the capacitor providing a coupling ratio greater than 1.0, the capacitor including a bottom plate and a top plate separated by a capacitor dielectric, wherein an electrical contact couples the bottom plate of the capacitor to a gate of the MOSFET; and
wherein the non-volatile memory cells are selectively programmed such that the non-volatile memory cells implement a logic function that selects an output line responsive to an address provided to the address lines. - View Dependent Claims (47, 48, 49, 50, 51, 52, 53, 54)
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55. An address decoder for a memory device, the address decoder comprising:
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a number of address lines;
a number of output lines;
wherein the address lines, and the output lines form an array;
a number of non-volatile memory cells that are disposed at intersections of output lines and address lines, wherein at least one non-volatile memory cell includes a metal oxide semiconductor field effect transistor (MOSFET) comprising a gate and a channel region separated by a gate oxide, a stacked capacitor formed according to a dynamic random access memory (DRAM) process, the capacitor providing a coupling ratio greater than 1.0, the capacitor including a bottom plate and a top plate separated by a capacitor dielectric, wherein an electrical contact couples the bottom plate of the capacitor to a gate of the MOSFET; and
wherein the non-volatile memory cells are selectively programmed such that the non-volatile memory cells implement a logic function that selects an output line responsive to an address provided to the address lines. - View Dependent Claims (56, 57, 58, 59, 60, 61, 62, 63)
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Specification