Semiconductor memory device having hierarchical word line structure

• US 6,452,862 B1
• Filed: 10/19/2001
• Issued: 09/17/2002
• Est. Priority Date: 10/23/2000
• Status: Expired due to Term

• Current Assignee: Panasonic Semiconductor Solutions Co., Ltd. (Winbond Electronics Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Tomotani, Hiroshi
• Primary Examiner(s): PHAN, TRONG Q
• Application Number:
  US09/981,981
• Publication Number:
  US 20020048210A1
• Time in Patent Office: 333 Days
• Field of Search: 365/230.03, 365/230.06, 365/203, 365/51, 365/63
• US Class Current: 365/230.06
• CPC Class Codes: G11C 11/418 Address circuits
• CPC Class Codes: G11C 8/10 Decoders
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection
• CPC Class Codes: G11C 8/14 Word line organisation; Word line lay-out

Abstract

The semiconductor memory device includes a memory cell array, a block selection circuit, a row decoder, a word driver, and a column decoder. The memory cell array includes a plurality of memory cells, a plurality of main word lines and a plurality of bit line pairs. The plurality of main word lines are provided corresponding to the rows, that is, m main word lines are provided per row (where m is an integer equal to or greater than two). The plurality of bit line pairs are provided corresponding to the columns. The memory cell array is divided into a plurality of memory blocks in the column direction. Each of the plurality of memory blocks further includes a plurality of sub word lines. The plurality of sub word lines are provided corresponding to the rows. Each of the plurality of sub word lines is connected to one of the m main word lines of the corresponding row.

Claims

1. A semiconductor memory device, comprising:

a memory cell array including a plurality of memory cells arranged in rows and columns, a plurality of main word lines arranged in the rows, and a plurality of bit line pairs arranged in the columns, wherein

m main word lines are arranged per row (where m is an integer equal to or greater than two), and

the memory cell array is divided into a plurality of memory blocks in the column direction, each of the plurality of memory blocks including a plurality of sub word lines arranged in the rows and each connected to one of the m main word lines arranged in the corresponding row, the semiconductor memory device further comprising;

a block selection circuit for selecting a corresponding one of the plurality of memory blocks in response to a column address signal;

a row decoder for selecting a corresponding row in response to a row address signal;

a word driver for activating one of the m main word lines, arranged in the row selected by the row decoder, which is connected to the sub word line included in the memory block selected by the block selection circuit; and

a column decoder for selecting a corresponding column in response to the column address signal.

2. The semiconductor memory device according to claim 1, further comprising:

n first input/output (I/O) line pairs (where n is a positive integer), wherein

the column decoder selects n columns from the memory block selected by the block selection circuit, in response to the column address signal, the semiconductor memory device further comprising;

a first column selection circuit for connecting bit line pairs corresponding to the n columns selected by the column decoder to the n first I/O line pairs.

3. The semiconductor memory device according to claim 2, wherein the column decoder further selects p first I/O line pairs from the n first I/O line pairs in response to the column address signal (where p is a positive integer), the semiconductor memory device further comprising:

p second I/O line pairs; and

a second column selection circuit for connecting the p first I/O line pairs selected by the column decoder to the p second I/O line pairs.

4. The semiconductor memory device according to claim 1, further comprising:

n first I/O line pairs (where n is a positive integer); and

p second I/O line pairs (where p is a positive integer), wherein

the column decoder selects n bit line pairs in response to the column address signal, the n bit line pairs including p bit line pairs included in the memory block selected by the block selection circuit, the semiconductor memory device further comprising;

a first column selection circuit for connecting the n bit line pairs selected by the column decoder to the n first I/O line pairs; and

a second column selection circuit for connecting to the p second I/O line pairs p first I/O line pairs of the n first I/O line pairs, which are connected to the p bit line pairs included in the memory block selected by the block selection circuit.

5. The semiconductor memory device according to claim 1, wherein each of a plurality of sub word lines included in one of the plurality of memory blocks and each of a plurality of sub word lines included in a memory block adjacent to the memory block are connected to one of the m main word lines arranged in the corresponding row through a common line.

6. The semiconductor memory device according to claim 1, further comprising a precharge circuit for precharging a plurality of bit line pairs included in the memory block selected by the block selection circuit to a prescribed potential.