Method and apparatus for providing a serial interface between an asynchronous transfer mode (ATM) layer and a physical (PHY) layer

• US 6,452,927 B1
• Filed: 12/29/1995
• Issued: 09/17/2002
• Est. Priority Date: 12/29/1995
• Status: Expired due to Term

• Current Assignee: RPX Corporation
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Rich, Craig S.
• Primary Examiner(s): Patel, Ajit
• Application Number:
  US08/581,242
• Time in Patent Office: 2,454 Days
• Field of Search: 370/395, 370/412, 370/366, 370/463, 341/100, 341/101, 364/916.1, 364/926.2, 364/926.5, 364/934, 364/934.1, 364/939, 364/939.5, 364/949.7, 364/950, 364/950.1, 364/950.2, 395/891
• US Class Current: 370/395.1
• CPC Class Codes: H04L 12/5601 Transfer mode dependent, e.g. ATM
• CPC Class Codes: H04L 2012/5604 Medium of transmission, e.g. fibre, cable, radio
• CPC Class Codes: H04L 49/3081 ATM peripheral units, e.g. policing, insertion or extraction

Abstract

An extender circuit provides a serial communication interface between an ATM layer and a PHY layer. The extender circuit includes a first circuit serially coupled to a second circuit. The first circuit communicates in parallel with the ATM layer, and the second circuit communicates in parallel with the PHY layer. The extender circuit additionally includes a serial link which serially transmits signals between the first and second circuits. The serial link includes a first serial link for transmitting a first serial signal from the first circuit to the second circuit, and a second serial link transmitting a second serial signal from the second circuit to the first circuit. The first circuit and the second circuit include similar architecture. The first circuit includes a parallel interface circuit for communicating in parallel with the ATM layer and a serial interface circuit coupled to the parallel interface circuit for serially communicating with the second circuit. The parallel interface circuit includes control circuitry, such as a programmable logic device, and memory circuitry, such as a first-in-first-out (FIFO) memory device. The serial interface circuit includes serializing/deserializing circuitry which includes serializing circuitry for serializing a plurality of parallel signals received from the parallel interface circuit and outputting a plurality of serial output signals. The serializing/deserializing circuitry further includes deserializing circuitry for deserializing a plurality of serial input signals to form a plurality of deserialized signals and providing the deserialized signals to the parallel interface circuit.

Claims

1. A communication system comprising:

an asynchronous transfer mode (ATM) layer;

a physical (PHY) layer; and

an extender circuit coupled to the ATM layer and the PHY layer, the extender circuit providing a serial communication interface between the ATM layer and the PHY layer, the extender circuit emulating an ATM layer interface at the PHY layer and a PHY layer interface at the ATM layer, wherein the extender circuit communicates in parallel with the ATM layer and with the PHY layer.

2. The communication system of claim 1, wherein the extender circuit comprises:

a first circuit coupled to the ATM layer and communicating in parallel with the ATM layer; and

a second circuit coupled to the PHY layer and communicating in parallel with the PHY layer, the second circuit coupled serially with the first circuit.

3. The communication system of claim 2, wherein the extender circuit further comprises a serial link, the serial link serially transmitting signals between the first and second circuit.

4. The communication system of claim 2, wherein the first circuit comprises:

a parallel interface circuit communicating in parallel with the ATM layer; and

a serial interface circuit coupled to the parallel interface circuit and serially communicating with the second circuit.

5. The communication system of claim 4, wherein the parallel interface circuit comprises:

control circuitry coupled to the ATM layer and the serial interface circuit; and

memory circuitry coupled to the ATM layer, the control circuitry and the serial interface circuit, the memory circuitry transmitting a plurality of signals to the ATM layer.

6. The communication system of claim 5, wherein the control circuitry comprises a programmable logic device.

7. The communication system of claim 5, wherein the memory circuitry comprises a first-in-first-out (FIFO) memory device.

8. An interface circuit comprising:

a parallel interface circuit configured to communicate in parallel with an asynchronous transfer mode (ATM) layer, the parallel interface circuit emulating a physical (PHY) layer interface at the ATM layer; and

a serial interface circuit coupled to the parallel interface circuit and configured to serially communicate with a serial bus.

9. The interface circuit of claim 8, wherein the parallel interface circuit comprises:

control circuitry coupled to the ATM layer and the serial interface circuit; and

memory circuitry coupled to the ATM layer, the control circuitry and the serial interface circuit, the memory circuitry transmitting a plurality of signals to the ATM layer.

10. The interface circuit of claim 9, wherein the control circuitry comprises a programmable logic device.

11. The interface circuit of claim 9, wherein the memory circuitry comprises a first-in-first-out (FIFO) memory device.

12. The interface circuit of claim 8, wherein the serial interface circuit comprises:

serializing/deserializing circuitry coupled to the parallel interface circuit and coupled serially with the serial bus, the serializing/deserializing circuitry serializing a plurality of parallel signals received from the parallel interface circuit and outputting a plurality of serial output signals, the serializing/deserializing circuitry further deserializing a plurality of serial input signals to form a plurality of deserialized signals and providing the plurality of deserialized signals to the parallel interface circuit.

13. The interface circuit of claim 12, wherein the serializing/deserializing circuitry comprises:

serializing circuitry serializing the plurality of parallel signals received from the parallel interface circuit and outputting a plurality of serial output signals; and

deserializing circuitry deserializing the plurality of serial input signals to form the plurality of deserialized signals and providing the plurality of deserialized signals to the parallel interface circuit.

14. An interface circuit comprising:

a parallel interface circuit configured to communicate in parallel with a physical (PHY) layer, the parallel interface circuit emulating an asynchronous transfer mode (ATM) layer interface at the PHY layer; and

a serial interface circuit coupled to the parallel interface circuit and configured to serially communicate with a serial bus.

15. The interface circuit of claim 14, wherein the parallel interface circuit comprises:

control circuitry coupled to the PHY layer and the serial interface circuit; and

memory circuitry coupled to the PHY layer, the control circuitry and the serial interface circuit, the memory circuitry transmitting a plurality of signals to the PHY layer,.

16. The interface circuit of claim 15, wherein the control circuitry comprises a programmable logic device.

17. The interface circuit of claim 15, wherein the memory circuitry comprises a first-in-first-out (FIFO) memory device.

18. The interface circuit of claim 14, wherein the serial interface circuit comprises:

serializing/deserializing circuitry coupled to the parallel interface circuit and coupled serially with the serial bus, the serializing/deserializing circuitry serializing a plurality of parallel signals received from the parallel interface circuit and outputting a plurality of serial output signals, the serializing/deserializing circuitry further deserializing a plurality of serial input signals to form a plurality of deserialized signals and providing the plurality of deserialized signals to the parallel interface circuit.

19. The interface circuit of claim 18, wherein the serializing/deserializing circuitry comprises:

serializing circuitry serializing a plurality of parallel signals received from the parallel interface circuit and outputting a plurality of serial output signals; and

deserializing circuitry deserializing a plurality of serial input signals to form a plurality of deserialized signals and providing the plurality of deserialized signals to the parallel interface circuit.

20. An extender circuit configured to provide a serial communication interface between an asynchronous transfer mode (ATM) layer and a physical (PHY) layer, the extender circuit comprising:

a first circuit configured to communicate in parallel with the ATM layer, the first circuit emulating a PHY layer interface at the ATM layer; and

a second circuit coupled serially to the first circuit, the second circuit configured to communicate in parallel with the PHY layer, the second circuit emulating an ATM layer interface at the PHY layer.

21. The extender circuit of claim 20, wherein the extender circuit further comprises a serial link, the serial link serially transmitting signals between the first and second circuit.

22. The extender circuit of claim 20, wherein the first circuit comprises:

a parallel interface circuit for communicating in parallel with the ATM layer; and

a serial interface circuit coupled to the parallel interface circuit and serially communicating with the second circuit.

23. The extender circuit of claim 22, wherein the parallel interface circuit comprises:

control circuitry coupled to the serial interface circuit; and

memory circuitry coupled to the control circuitry and the serial interface circuit, the memory circuitry for transmitting a plurality of signals to the ATM layer.

24. The extender circuit of claim 23, wherein the control circuitry comprises a programmable logic device.

25. The communication system of claim 23, wherein the memory circuitry comprises a first-in-first-out (FIFO) memory device.

29. The method of claim 22, further comprising the step of:

signaling a second flag condition when the memory circuit contains a second predetermined number of the second plurality of parallel signals.

30. The method of claim 29, further comprising the step of:

generating a second control code in response to the memory circuit signaling the second flag condition;

serializing the second control code to form a second serialized control code; and

transmitting the second serialized control code between the ATM layer and the PHY layer, wherein the second control signal enables the transmission of the first plurality of data signals between the ATM layer and the PHY layer.

26. In a communication system having an extender circuit providing a serial communication interface between an asynchronous transfer mode (ATM) and a physical (PHY) layer, a method for transmitting a plurality of signals between the ATM layer and the PHY layer, the method comprising the steps of:

serializing a first plurality of parallel signals to form a first plurality of serial signals;

transmitting the first plurality of serial signals between the ATM layer and the PHY layer; and

deserializing the first plurality of serial signals to form a second plurality of parallel signals,

wherein the extender circuit emulates an ATM layer interface at the PHY layer and a PHY layer interface at the ATM layer, and wherein the extender circuit communicates in parallel with the ATM layer and with the PHY layer while serially communicating between the ATM layer and the PHY layer.

27. The method of claim 26, wherein the extender circuit includes a memory circuit for storing the second plurality of parallel signals, further comprising the steps of:

providing the second plurality of parallel signals to the memory circuit;

outputting the second plurality of parallel signals from the memory circuit; and

signaling a first flag condition when the memory circuit contains a first predetermined number of the second plurality of parallel signals.

28. The method of claim 27, further comprising the steps of:

generating a first control code in response to the memory circuit signaling the first flag condition;

serializing the first control code to form a first serialized control code; and

transmitting the first serialized control code between the ATM layer and the PHY layer, wherein the first control signal disables the transmission of the first plurality of signals between the ATM layer and the PHY layer.