Encoding/decoding system for coherent signal interference reduction

• US 6,452,980 B1
• Filed: 01/10/2000
• Issued: 09/17/2002
• Est. Priority Date: 01/10/2000
• Status: Expired due to Term

• Current Assignee: Secom Company Limited, SRI International, Inc.
• Original Assignee: Secom Company Limited, Sarnoff Corporation (SRI International, Inc.)
• Inventors: Zalud, Peter, Evans, Robert, Lin, Min-Long, Schepps, Jonathan
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): Fan, Chieh M.
• Application Number:
  US09/480,776
• Time in Patent Office: 981 Days
• Field of Search: 375/282, 375/285, 375/296, 375/333, 375/340, 342/42, 342/44, 342/45, 342/51, 340/825.34, 340/505, 340/10.1, 340/10.3, 340/10.4, 340/10.42
• US Class Current: 375/285
• CPC Class Codes: G07C 9/28 the pass enabling tracking or indicating presence
• CPC Class Codes: H03M 5/12 Biphase level code, e.g. split phase code, Manchester code; Biphase space or mark code, e.g. double frequency code

Abstract

An apparatus is described for reducing coherent signal interference between at least two bit streams framed with a common clock signal. The apparatus includes an internal clock signal generated from the common clock signal and a Manchester encoder for encoding the internal clock signal with a unique signature. Also included is a logic AND-gate for combining one bit stream of the two bit streams with the encoded clock signal to produce an encoded output signal. When the encoded output signal is combined with another of the two bit streams during transmission, individual bits of the combined bit streams are identifiable at a receiving end. The receiving end decodes the combined bit streams and properly discriminates between ONEs and ZEROs.

Claims

1. An apparatus for reducing coherent signal interference between at least two bit streams, each bit stream having been framed with a common clock signal, comprising

an internal clock signal generated from the common clock signal,

an encoder for encoding the internal clock signal with a unique signature,

a logic AND gate for combining one bit stream of the at least two bit streams with the encoded internal clock signal to produce an encoded output signal,

wherein when the encoded output signal is combined with another of the at least two bit streams during transmission, individual bits of the combined bit streams are identifiable at a receiving end.

2. The apparatus of claim 1 wherein the encoder includes a Manchester encoder for encoding the internal clock signal.

3. The apparatus of claim 1 wherein the encoder includes a re-circulating shift register having a serial output terminal, a serial input terminal, a parallel input terminal and a clock input terminal,

wherein a serial output signal of the serial output terminal of the shift register is fed back to the serial input terminal,

the internal clock signal is provided to the clock input terminal,

the unique signature is provided to the parallel input terminal, and

an exclusive-OR circuit combines the serial output signal of the shift register and the internal clock signal to produce the encoded clock signal.

4. The apparatus of claim 3 wherein the unique signature is a user selected bit pattern, and is loaded into the parallel input terminal of the shift register once during initialization.

5. The apparatus of claim 4 wherein the shift register has a length equal to a length of the user selected bit pattern, and

the bit pattern is re-circulated once for every bit time period.

6. Apparatus for interrogating/identifying a plurality of coded tags comprising

an interrogator/reader (I/R) for transmitting, at a carrier frequency to the tags, bit streams of data and for receiving response bit streams of data from the tags,

the plurality of coded tags, each of the tags (a) storing a unique signature pattern and (b) generating bit streams of data for responding to the I/R,

a clock signal generated by each tag from the carrier frequency,

an encoder in each tag for encoding the clock signal with the unique signature pattern, and

a circuit in each tag for modulating the encoded clock signal with the generated bit streams to produce the response bit streams from each tag.

7. The apparatus of claim 6 wherein the encoder includes a Manchester encoder for encoding the clock signal.

8. The apparatus of claim 6 wherein the encoder includes a re-circulating shift register having a serial output terminal, a serial input terminal, a parallel input terminal and a clock input terminal,

wherein a serial output signal of the serial output terminal of the shift register is fed back to the serial input terminal,

the clock signal is provided to the clock input terminal, and

the signature pattern is provided to the parallel input terminal, and

an exclusive-OR circuit combines the serial output signal of the shift register and the clock signal to produce the encoded clock signal.

9. The apparatus of claim 8 wherein the shift register has a length equal to a length of the signature pattern, and

the signature pattern is re-circulated once for every bit time period.

10. A discriminator circuit for decoding a bit stream of pulses framed with a common clock signal, comprising

a receiver for receiving the bit stream of pulses, wherein a predetermined number of pulses in the bit stream of pulses are contained in a bit time period of ONEs and ZEROs,

clock pulses generated from the common clock signal and having a frequency value that is a multiple value of the frequency of the common clock signal,

a first counter receiving the bit stream of pulses and counting the clock pulses, the first counter determining that a ONE is present in the bit stream of pulses when counting up to a predetermined value, and

a second counter receiving the bit stream of pulses and counting the clock pulses, the second counter determining that a ZERO is present in the bit stream of pulses when counting up to the predetermined value.

11. The circuit of claim 10 wherein each counter is free running and counting clock pulses, being reset by each pulse in the bit stream, and

the circuit includes a control sequencer for synchronizing a start time for counting the clock pulses.

12. The circuit of claim 11 wherein each pulse in the bit stream has a duration that is less than or equal to the bit time period and the first counter determines that a ONE is present when at least one pulse in the bit stream resets the first counter during the bit time period, and

the second counter determines that a ZERO is present when pulses in the bit stream do not reset the second counter during the bit time period.

13. The circuit of claim 10 wherein the receiver includes a threshold comparator for converting the bit stream of pulses to a logic level compatible for the first and second counters.

14. Apparatus for interrogating/identifying coded tags, including an interrogator/reader (I/R) for transmitting, at a carrier frequency, to the tags, bit streams of data and for receiving response bit streams of data from each tag, the response bit streams of data including ONEs and ZEROs, the apparatus comprising

a receiver for receiving the response bit streams of data, wherein the response bit streams include data framed with a common clock signal,

an internal clock signal generated from the common clock signal and having a frequency value that is a multiple value of the frequency of the common clock signal,

a first counter receiving the response bit streams of data and responsive to the clock signal, the first counter providing an output signal when at least one bit of data is present in the response bit streams of data during a predetermined interval, and

a second counter receiving the response bit streams of data and clocked by the clock signal, the second counter providing an output signal when no bits of data are present in the response bit streams of data during the predetermined interval,

wherein when the first counter provides the output signal, a ONE is present in the bit streams of data and when the second counter provides the output signal, a ZERO is present in the bit streams of data.

15. The circuit of claim 14 wherein the receiver includes a threshold comparator for converting the bit stream to a logic level compatible with the first and second counters.

16. The circuit of claim 14 wherein each of the first and second counters is free running and counts pulses of the clock signal, and

the circuit includes a control sequencer for synchronizing a start time for counting the pulses of the clock signal.

17. The circuit of claim 16 wherein each bit of data in the bit stream has a duration that is less than or equal to the predetermined interval, and the first counter provides the output signal when at least one bit of data in the bit stream is present during the predetermined interval, and

the second counter provides the output signal when bits of data are not present during the predetermined interval.