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Encoding/decoding system for coherent signal interference reduction

  • US 6,452,980 B1
  • Filed: 01/10/2000
  • Issued: 09/17/2002
  • Est. Priority Date: 01/10/2000
  • Status: Expired due to Term
First Claim
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1. An apparatus for reducing coherent signal interference between at least two bit streams, each bit stream having been framed with a common clock signal, comprisingan internal clock signal generated from the common clock signal, an encoder for encoding the internal clock signal with a unique signature, a logic AND gate for combining one bit stream of the at least two bit streams with the encoded internal clock signal to produce an encoded output signal, wherein when the encoded output signal is combined with another of the at least two bit streams during transmission, individual bits of the combined bit streams are identifiable at a receiving end.

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