Timing closure methodology

• US 6,453,446 B1
• Filed: 04/02/1998
• Issued: 09/17/2002
• Est. Priority Date: 12/24/1997
• Status: Expired due to Fees

• Current Assignee: Synopsys Incorporated
• Original Assignee: Magma Design Automation (Synopsys Incorporated)
• Inventors: van Ginneken, Lukas P. P. P.
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Speight, Jibreel
• Application Number:
  US09/054,379
• Time in Patent Office: 1,629 Days
• Field of Search: 716/19, 716/8, 716/6, 716/9, 716/2, 716/3, 703/19, 713/503
• US Class Current: 716/114
• CPC Class Codes: G06F 2119/12 Timing analysis or timing optimisation
• CPC Class Codes: G06F 30/27 using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement

Abstract

An automated method for designing an integrated circuit layout using a computer based upon an electronic circuit description and based upon cells which are selected from a cell library, each of the cells having an associated area, comprising the steps of: (a) placing each of the cells in the integrated circuit layout so that the cells can be coupled together by wires to form a circuit path having an associated predetermined delay constraint wherein the cells are coupled together based upon the electronic circuit description input to the computer; (b) connecting the cells together with the wires to form the circuit path; and (c) adjusting an area of at least one of the cells to satisfy the associated predetermined delay constraint of the circuit path.

Claims

1. An automated method for designing an initial integrated circuit layout of a digital circuit with a computer, based upon an electronic circuit description and by using a cell library containing cells, comprising the steps of:

(a) selecting a plurality of cells from the cell library that are intended to be coupled to each other with a plurality of wires and that can be used to implement the digital circuit based on the electronic circuit description input to the computer to obtain a selected plurality of cells, at least some of the selected plurality of cells having an initial intended delay associated therewith for ensuring that predetermined timing constraints are met;

(b) determining a placement of the selected plurality of cells and the wires coupled thereto using a sequence of instructions from the computer program; and

(c) determining the area of the some cells, the area of each some cell being determined using the lengths of the wires coupled to each of said some cells such that the initial intended delay of each some cell is realized, the length of each wire being determined by the placement of the cells coupled to that wire.

2. The automated method of claim 1 further comprising:

routing the digital circuit to generate the integrated circuit layout.

3. The automated method of claim 2 wherein,

prior to the step of routing, the area and placement of each of the selected plurality of cells and the lengths of the wires is finalized.

4. The method of claim 1 wherein the plurality of cells are coupled to each other based on the electronic circuit description input to the computer.

5. The automated method of claim 1 wherein each of the plurality of wires has an associated capacitive load value;

and

wherein each wire is associated with a net weight value that represents the sensitivity of the total area of the digital circuit of step (a) with respect to the associated capacitive load value of the wire.

6. The automated method of claim 5 wherein the net weight w_i of the wire coupled to a selected cell is:

7. The automated method of claim 6 wherein the determined areas of said some selected cells are chosen based upon the product of the net weight w_i and the net load C_i in order to meet said predetermined timing constraints.

8. The automated method of claim 1 wherein all of the selected cells have an initial intended delay associated therewith.

9. The automated method of claim 8 wherein the step of determining determines the area of all of the selected cells.

10. The automated method of claim 1 further comprising

step of inserting a buffer in one of the wires after the step of determining the placement and before the step of determining the area.

11. The automated method of claim 10 wherein the step of inserting the buffer comprises:

determining the wire into which a the buffer can be inserted while still meeting the predetermined timing constraints; and

inserting the buffer into the wire if area will be saved by the insertion.

12. The automated method of claim 1 further comprising:

stretching the initial intended delay of a selected cell to decrease the area of the selected cell after the step of determining the placement and before the step of determining the area.

13. The automated method of claim 1 further comprising:

stretching the initial intended delays of a plurality of selected cells coupled to each other to decrease the area of each of the coupled cells after the step of determining the placement and before the step of determining the area.

14. The automated method of claim 1 further comprising:

compressing the initial intended delay of a selected cell after the step of determining the placement and before the step of determining the area.

15. The automated method of claim 14 wherein the compressing step is limited by a gain requirement of the selected cell.

16. The automated method of claim 1 further comprising:

compressing the initial intended delays of a plurality of the selected cells after the step of determining the placement and before the step of determining the area.

17. The automated method of claim 1 wherein a group of said some cells are assigned in buckets and operated upon.

18. The automated method of claim 17 wherein the group of said some cells ranges from 20 to 200 cells.

19. An integrated circuit layout produced in accordance with the automated method of claim 1.

20. The method according to claim 1 wherein the cell library for each of the some cells selected does not include the area of each of the some cells.

21. An automated method for designing an integrated circuit layout using a computer, based upon an electronic circuit description and based upon cells which are selected from a cell library, comprising the steps of:

(a) placing each of the cells in the integrated circuit layout and wires associated therewith so that the cells can be coupled together by wires to form a circuit path having an associated predetermined timing constraint wherein the cells are coupled together by wires based upon the electronic circuit description input to the computer, the electronic circuit description including an initial intended delay associated with each cell; and

(b) determining an area of at least some of the cells to satisfy the associated predetermined timing constraint of the circuit path, the area being determined as a function of the ratio of the input capacitance and output capacitance of the wires coupled to each of said some cells such that the initial intended delay of each cell is realized.

22. The automated method of claim 21 wherein each of the wires has an associated capacitive load value;

and

wherein each wire is associated with a net weight value that represents the sensitivity of the total area of the integrated circuit layout with respect to the associated capacitive load value of the wire.

23. The automated method of claim 22 wherein the net weight w_i of the wire coupled to a cell is:

24. The automated method of claim 23 wherein the areas of at least some of the cells are chosen based upon the product of the net weight w_i and the net load C_i in order to meet said predetermined timing constraints.

25. The automated method of claim 24 wherein the length of each wire is determined by the placement of the cells coupled to that wire.

26. The automated method of claim 21 wherein the length of each wire is determined by the placement of the cells coupled to that wire.

27. The automated method of claim 21 further comprising:

inserting a buffer in one of the wires after the step of placing and before the step of determining the area.

28. The automated method of claim 21 further comprising:

stretching the associated relative delay value of a selected cell after the step of placing and before the step of determining the area.

29. The automated method of claim 21 further comprising:

compressing the associated relative delay value of a selected cell after the step of placing and before the step of determining the area.

30. The automated method of claim 29 wherein the compressing step is limited by a gain requirement of the selected cell.

31. The automated method of claim 21 wherein a group of said some cells are assigned in buckets and operated upon in order to determined the initial intended area of each of the group of said some cells.

32. The automated method of claim 31 wherein the group of said some cells ranges from 20 to 200 cells.

33. The automated method of claim 21 wherein the step of determining determines the area of all of the selected cells.

34. The method according to claim 21 wherein the electronic circuit description used to placing each of the cells in the integrated circuit layout does not include the area of the cells.

35. An automated method for designing an integrated circuit layout of a circuit of at least four cells coupled to each other with a plurality of wires by using a computer and based upon an electronic circuit description containing information on the digital circuit, comprising the steps of:

(a) selecting a plurality of cells which can be used to implement the digital circuit based upon the electronic circuit description, each of the plurality of cells having an associated load and an initial intended delay associated therewith for ensuring that predetermined timing constraints are met, the selected plurality of cells comprising at least a first cell having a first load, a second cell having a second load, a third cell having a third load, and a fourth cell having a fourth load;

(b) determining initial placement locations for each of the selected plurality of cells, including the first cell, the second cell, the third cell, and the fourth cell;

(c) setting the size of each of the selected plurality of cells and the loads of each cell so that the predetermined timing constraints are met, the size of each cell being determined using the lengths of the wires coupled to each of said cells such that the initial intended delay of each cell is realized, the length of each wire being determined by the placement of the cells coupled to that wire.

36. The automated method of claim 35 wherein each of the load has an associated capacitive load value;

and

wherein each load is associated with a net weight value that represents the sensitivity of the total area of the integrated circuit layout with respect to the associated capacitive load value of the load.

37. The automated method of claim 36 wherein the net weight w_i of the load coupled to a cell is:

38. The automated method of claim 37 wherein the areas of at least some of the cells are chosen based upon the product of the net weight w_i and the net load C_i in order to meet said predetermined timing constraints.

39. The method according to claim 35 wherein the plurality of cells are selected without having a size associated therewith.

40. A method according to claim 35 in which each of the first, second, third and fourth cells implement at least one logic operation.

41. A method according to claim 35 which none of the first, second, third and fourth cells are buffers.

42. An integrated circuit layout produced in accordance with the automated method of claim 35.

43. An automated method for determining an integrated circuit layout of at least four cells by using a computer and based upon an electronic circuit description containing information on the digital circuit, the automated method comprising the steps of:

(a) selecting a plurality of cells which can be used to implement the digital circuit using the electronic circuit description, the plurality of cells comprising a first cell having a first load and a first initial intended delay, a second cell connected to the first cell and having a second load and a second initial intended delay associated therewith, a third cell connected to the second cell and having a third load and a third initial intended delay associated therewith, and a fourth cell connected to the third cell and having a fourth load and a fourth initial intended delay associated therewith, the digital circuit having predetermined timing constraints;

(b) determining the placement locations for each of the selected plurality of cells including the first cell, the second cell, the third cell, and the fourth cell and wires associated therewith;

(c) selecting the size of the first cell based on the first load of the first cell so that the first initial intended delay is realized, the size of the first cell being determined using the lengths of the wires coupled to the first cell, the length of each wire being determined by the placement of the cells coupled to that wire;

(d) selecting the size of the second cell based on the second load of the second cell so that the second initial intended delay is realized, the size of the second cell being determined using the lengths of the wires coupled to the second cell, the length of each wire being determined by the placement of the cells coupled to that wire;

(e) selecting the size of the third cell based on the third load so that the third initial intended delay is realized, the size of the third cell being determined using the lengths of the wires coupled to the third cell, the length of each wire being determined by the placement of the cells coupled to that wire; and

(f) selecting the size of the fourth cell based on the fourth load so that the fourth initial intended delay is realized, the size of the fourth cell being determined using the lengths of the wires coupled to the fourth cell, the length of each wire being determined by the placement of the cells coupled to that wire, wherein the selection of the area of the first, second, third and fourth cells ensures that the predetermined timing constraints associated therewith are met.

44. An integrated circuit layout produced in accordance with the automated method of claim 43.

45. A method according to claim 43 further including the step of routing the digital circuit.

46. A method according to claim 43 in which each of the first, second, third and fourth cells implement at least one logic operation.

47. A method according to claim 43 in which none of the first, second, third and fourth cells are buffers.

48. The method according to claim 43 wherein the plurality of cells are selected without having a size associated therewith.

49. An automated method of modeling the delay of the cells of an integrated circuit comprising the steps of:

associating an initial gain value with each cell that has been initially selected for inclusion in the integrated circuit;

computing the initial intended delay value of each cell based on the initial intended gain value.

50. The automated method of claim 49, wherein the initial intended gain value is determined such that the variation in the variable component of the initial intended delay is the same for all the cells in the circuit is minimized.

51. The automated method of claim 49, wherein the associated gain value of one or more cells are reduced to compress the associated relative delay value of said cells to assist in satisfying the predetermined timing constraints.

52. The automated method of claim 49, wherein the associated gain value of one or more cells are increased to stretch the associated relative delay value of said cells to assist in reducing the area of said cells.

53. The automated method of claim 52, further including the step of computing the input capacitance of each cell, the input capacitance being computed as the capacitive output load of said cell divided by the gain.

54. The automated method of claim 53, further including the step of computing the area of each cell, the area of each cell being computed as the capacitive output load of said cell times the net weight of each cell.