Double LDD devices for improved dram refresh

• US 6,455,362 B1
• Filed: 08/22/2000
• Issued: 09/24/2002
• Est. Priority Date: 08/22/2000
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Tran, Luan C., Kerr, Robert, McQueen, Mark
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Nhu, David
• Application Number:
  US09/642,780
• Time in Patent Office: 763 Days
• Field of Search: 438/194, 438/197, 438/230, 438/231, 438/232, 438/301, 438/305, 438/306, 438/309, 438/289, 438/332, 438/570
• US Class Current: 438/194
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures

Abstract

An integrated circuit device with improved DRAM refresh characteristics, and a novel method of making the device, is provided. A semiconductor substrate is provided with gate structures formed on its surface in each of an array portion and a peripheral portion. Single lightly doped regions are formed adjacent to the channel regions by ion implantation in the substrate. Dielectric spacers having a first width are formed on the substrate surface adjacent to the gate structures covering at least a portion of the single lightly doped regions. Heavily-doped regions are ion-implanted on opposite sides of the gate structure in the peripheral portion. The dielectric spacers are etched back to a second width smaller than the first width. Double lightly doped regions are formed by ion implantation in the substrate in an area of the substrate left exposed by the spacer etch back. Triple lightly doped regions may be also be formed by a first implant at the gate edge, a second implant through an intermediate spacer, and a third implant after the spacer etch back.

Claims

1. A method of forming an access transistor of a memory cell, said method comprising:

forming a gate structure on a substrate, said gate structure defining a channel region of said access transistor;

forming single lightly doped regions on opposite sides of said gate structure and adjacent said channel region;

subsequently forming spacers on the sides of said gate structure;

forming heavily doped regions adjacent said single lightly doped regions; and

forming double lightly doped regions between each of said single lightly doped regions and said heavily doped regions.

2. The method of claim 1 wherein said channel region is doped with a doping concentration up to about 30% less than a doping concentration of a channel region of an access transistor not having said single and double lightly doped regions.

3. The method of claim 1, further comprising forming a dielectric layer on said gate structure and said substrate before forming said single lightly doped region.

4. The method of claim 1 further comprising forming a dielectric layer on said gate structure and said substrate after forming said single lightly doped region.

6. The method of claim 3 wherein said forming of said dielectric layer includes depositing oxide to a thickness of between about 30 and about 200 angstroms.

7. The method of claim 3 wherein said forming of said dielectric layer includes depositing nitride to a thickness of between about 30 and about 200 angstroms.

8. The method of claim 3 wherein said forming of said dielectric layer includes depositing oxynitride to a thickness of between about 30 and about 200 angstroms.

9. The method of claim 3 wherein said forming of said dielectric layer includes depositing tetraethylorthosilicate (TEOS) to a thickness of between about 30 and about 200 angstroms.

14. The method of claim 1 further comprising forming a conductive plug overlying at least said double lightly doped region.

15. The method of claim 3 further comprising forming a conductive plug overlying at least said double lightly doped region.

5. A method of forming an access transistor of a memory cell, said method comprising:

forming a gate structure on a substrate, said gate structure defining a channel region of said access transistor;

forming double lightly doped regions on opposite sides of said gate structure;

forming single lightly doped regions between each of said double lightly doped regions and said channel region; and

forming a triple lightly doped region in said substrate adjacent said double lightly doped region, wherein said double lightly doped region lies between said single lightly doped region and said triple lightly doped region.

10. The method of claim 5 wherein said forming of said dielectric layer includes depositing oxide to a thickness of between about 30 and about 200 angstroms.

11. The method of claim 5 wherein said forming of said dielectric layer includes depositing nitride to a thickness of between about 30 and about 200 angstroms.

12. The method of claim 5 wherein said forming of said dielectric layer includes depositing oxynitride to a thickness of between about 30 and about 200 angstroms.

13. The method of claim 5 wherein said forming of said dielectric layer includes depositing tetraethylorthosilicate (TEOS) to a thickness of between about 30 and about 200 angstroms.

16. A method of forming an access transistor of a memory cell, said method comprising:

forming a gate structure on a substrate, said gate structure defining a channel region of said access transistor;

forming double lightly doped regions on opposite sides of said gate structure;

forming single lightly doped regions between each of said double lightly doped regions and said channel region;

forming a triple lightly doped region in said substrate adjacent said double lightly doped region, wherein said double lightly doped region lies between said single lightly doped region and said triple lightly doped region; and

forming a conductive plug overlying at least said triple lightly doped region.

17. A method of forming an access transistor of a memory cell, said method comprising:

forming a gate structure of said access transistor on a substrate, said gate structure defining a channel region of said access transistor;

performing a first lightly doped implant on each side of said gate structure;

forming side spacers on the sides of said gate structure subsequent to performing said first lightly doped implant;

performing a second lightly doped implant on each side of said gate structure and associated spacers to produce double lightly doped source and drain regions of said access transistor, each of which has a single lightly doped region between it and said channel region.

18. A method of forming at least one access transistor of a memory cell in an array portion of a memory device and another transistor of a peripheral circuit portion of said memory device, said method comprising:

forming a first gate structure of said access transistor in said memory array portion and a second gate structure of said another transistor in said peripheral circuit portion on a substrate, said first and second gate structures defining respective channel regions of said access transistor and said another transistor;

performing a first lightly doped implant on each side of said first and second gate structures;

subsequently forming spacers on the sides of said first and second gate structures;

masking said memory array portion;

performing a heavily doped implant on each side of said second gate structure;

removing the masking of said memory array portion;

reducing the width of said spacers on the sides of said first and second gate structures; and

performing a second lightly doped implant on each side of said first and second gate structures.

19. The method of claim 18 wherein said first and second gate structures are formed at a same time.

20. The method of claim 18 further comprising performing a halo implant on each side of said second gate structure through a sidewall spacer after said memory array portion is masked and before performing said heavily doped implant.