Methods of fabricating scaled MOSFETs

• US 6,455,383 B1
• Filed: 10/25/2001
• Issued: 09/24/2002
• Est. Priority Date: 10/25/2001
• Status: Expired due to Fees

• Current Assignee: Silicon-Based Technology Corporation
• Original Assignee: Silicon-Based Technology Corporation
• Inventors: Wu, Ching-Yuan
• Primary Examiner(s): Jackson, Jerome
• Assistant Examiner(s): Rao, Shrinivas H.
• Application Number:
  US10/045,249
• Time in Patent Office: 334 Days
• Field of Search: 438/296, 438/303, 438/305, 438/592, 438/595, 438/596
• US Class Current: 438/296
• CPC Class Codes: H01L 21/28061 the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction H01L21/28052 takes precedence
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 29/4941 with a barrier layer between the silicon and the metal or metal silicide upper layer, e.g. Silicide/TiN/Polysilicon
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers

Abstract

The scaled MOSFETs having a conductive barrier-metal layer sandwiched between a metal layer or a thick silicide layer on the top and a first conductive gate layer at the bottom are disclosed by the present invention, in which the first conductive gate layer is etched to form a steep-gate structure or a taper-gate structure. The metal layer is encapsulated by a second masking dielectric layer formed on the top and a first dielectric spacer formed on both sides, no interaction would occur between the metal layer and the first conductive gate layer, a highly-conductive nature of the metal layer for gate interconnection can be preserved. A thick silicide layer is formed by a two-step self-aligned silicidation process and a conductive barrier-metal layer is formed to eliminate the interaction between the thick silicide layer and the first conductive gate layer, a highly conductive nature of the thick silicide layer for gate interconnection can be obtained. Moreover, the field-emission between the gate and the shallow moderately doped source/drain diffusion region can be minimized by a graded gate-oxide layer formed near the gate edges and the field emission between the trench corners of the semiconductor substrate and the gate can be completely eliminated by a flat shallow-trench-isolation structure.

Claims

1. A method of fabricating a scaled MOSFET, comprising the steps of:

providing a semiconductor substrate;

forming a flat shallow-trench-isolation(STI) structure over said semiconductor substrate having an active region and an isolation region, wherein said active region has a first conductive gate layer formed over a thin gate-dielectric layer and said isolation region is filled with planarized field-oxides;

depositing sequentially a conductive barrier-metal layer, a metal layer, and a second masking dielectric layer over said flat STI structure;

pattering a gate line over said flat STI structure to form a gate region on said active region and a gate-interconnection region on said planarized field-oxides by selectively etching said second masking dielectric layer, said metal layer, and said conductive barrier-metal layer in sequence;

forming a first dielectric spacer over sidewalls of said gate line;

etching back said planarized field-oxides outside of said first dielectric spacer to a depth slightly smaller than a thickness of said first conductive gate layer;

etching anisotropically said first conductive gate layer to form a gate structure;

forming a first poly-oxide layer over sidewalls of said gate structure and a thicker oxide layer over each side portion of said active region having a graded gate-oxide layer formed near gate edges;

implanting a moderate dose of doping impurities having a dopant type opposite to that of said semiconductor substrate into said side portion of said active region in a self-aligned manner to form a shallow moderately-doped source/drain diffusion region;

performing a pocket (halo) implant having a dopant type opposite to that of said shallow moderately-doped source/drain diffusion region to form a punch-through stop in said side portion of said active region;

forming a second dielectric spacer over sidewalls of said first dielectric spacer and said first poly-oxide layer;

implanting a high dose of doping impurities having a dopant type opposite to that of said semiconductor substrate into said side portion of said active region outside of said second dielectric spacer in a self-aligned manner to form a deeper heavily-doped source/drain diffusion region;

performing a rapid-thermal-annealing process to redistribute implanted doping impurities with an extension portion of said shallow moderately-doped source/drain diffusion region formed under said graded gate-oxide layer;

removing said thicker oxide layer and simultaneously etching said planarized field-oxides outside of said second dielectric spacer in a self-aligned manner to form a self-aligned source/drain contact hole over said deeper heavily-doped source/drain diffusion region; and

forming a self-aligned conductive layer over said deeper heavily-doped source/drain diffusion region through said self-aligned source/drain contact hole.

2. The method of claim 1, wherein said semiconductor substrate is a p-well or a p-type semiconductor substrate for fabricating an n-channel MOSFET or is an n-well or an n-type semiconductor substrate for fabricating a p-channel MOSFET.

3. The method of claim 1, wherein said conductive barrier-metal layer is preferably a refractory metal-nitride layer.

4. The method of claim 1, wherein said metal layer is preferably a high melting-point metal layer such as tungsten (W) or tungsten silicide (WSi₂).

5. The method of claim 1, wherein said first conductive gate layer is made of amorphous-silicon or polycrystalline-silicon implanted with n-type dopants for fabricating said n-channel MOSFET or implanted with p-type dopants for fabricating said p-channel MOSFET.

6. The method of claim 1, wherein said gate structure can be a steep-gate structure or a taper-gate structure having a taper angle between about 45 degrees and 90 degrees.

7. The method of claim 1, wherein said second masking dielectric layer is preferably made of silicon-nitrides or oxynitrides and said first dielectric spacer or said second dielectric spacer is preferably made of silicon-nitrides.

8. The method of claim 1, wherein said self-aligned conductive layer is preferably a refractory metal-silicide layer.

17. The method of claim 1 or claim 9, wherein said flat STI structure is fabricated by the steps comprising:

forming a multilayer structure over said semiconductor substrate by sequentially forming said thin gate-dielectric layer, said first conductive gate layer, and said first masking dielectric layer;

implanting a high dose of doping impurities having a dopant type opposite to that of said semiconductor substrate into said first conductive gate layer;

patterning said multilayer structure to define said active region by sequentially etching said first masking dielectric layer, said first conductive gate layer, and said thin gate-dielectric layer outside of said active region;

etching anisotropically said semiconductor substrate to form a shallow trench by using said first masking dielectric layer as an etching hard mask;

oxidizing sidewalls of said first conductive gate layer and a semiconductor surface of said shallow trench;

depositing a thick field-oxide film over said shallow trench and planarizing said thick field-oxide film using chemical-mechanical polishing (CMP) with said first masking dielectric layer as a polishing stop to form planarized field-oxides; and

etching back said planarized field-oxides to a depth equal to a thickness of said first masking dielectric layer followed by removing said first masking dielectric layer to form said flat shallow-trench-isolation structure.

18. The method of claim 1 or claim 9, wherein said flat shallow-trench-isolation structure is fabricated by the steps comprising:

forming a multilayer structure over said semiconductor substrate by sequentially forming said thin gate-dielectric layer, said first conductive gate layer, and said first masking dielectric layer;

implanting a high-dose of doping impurities having a dopant type opposite to that of said semiconductor substrate into said first conductive gate layer;

patterning said multilayer structure to define said active region by sequentially etching said first masking dielectric layer, said first conductive gate layer, and said thin gate dielectric layer;

forming a thin silicon-oxide spacer over sidewalls of said first masking dielectric layer, said first conductive gate layer, and said thin gate dielectric layer;

etching anisotropically said semiconductor substrate to form a shallow trench by using said first masking dielectric layer and said thin silicon-oxide spacer as an etching hard mask;

oxidizing a semiconductor surface of said shallow trench to form a thin thermal-oxide layer;

depositing a thick field-oxide film over said shallow trench and planarizing said thick field-oxide film using chemical-mechanical polishing with said first masking dielectric layer as a polishing stop to form planarized field-oxides; and

etching back said planarized field-oxides and said silicon-oxide spacer to a depth equal to a thickness of said first masking dielectric layer followed by removing said first masking dielectric layer to form said flat STI structure.

19. The method of claim 17 or claim 18, wherein said first masking dielectric layer is preferably made of silicon-nitrides.

20. The method of claim 17 or claim 18, wherein said thin gate dielectric layer is preferably a thermal-oxide layer or a nitrided thermal-oxide layer.

9. A method of fabricating a scaled MOSFET, comprising the steps of:

providing a semiconductor substrate;

forming a flat shallow-trench-isolation(STI) structure over said semiconductor substrate having an active region and an isolation region, wherein said active region has a first conductive gate layer formed over a thin gate-dielectric layer and said isolation region is filled with planarized field-oxides;

depositing sequentially a conductive barrier-metal layer, a second conductive gate layer, and a second masking dielectric layer over said flat STI structure;

patterning a gate line over said flat STI structure to form a gate region on said active region and a gate-interconnection region on said planarized field-oxides by selectively etching said second masking dielectric layer, said second conductive gate layer, and said conductive barrier-metal layer in sequence)

etching back said planarized field-oxides to a depth slightly smaller than a thickness of said first conductive gate layer;

etching anisotropically said first conductive gate layer to form a gate structure;

forming a first poly-oxide layer over sidewalls of said gate structure, a second poly-oxide layer over sidewalls of said second conductive gate layer, and a thicker oxide layer over each side portion of said active region having a graded gate-oxide layer formed near gate edges;

implanting a moderate dose of doping impurities having a dopant type opposite to that of said semiconductor substrate into said side portion of said active region in a self-aligned manner to form a shallow moderately-doped source/drain diffusion region;

performing a pocket (halo) implant having a dopant type opposite to that of said shallow moderately-doped source/drain diffusion region to form a punch-through stop in said side portion of said active region;

removing said second masking dielectric layer over said second conductive gate layer;

forming a first dielectric spacer over sidewalls of said second poly-oxide layer, said conductive barrier-metal layer, and said first poly-oxide layer;

implanting a high dose of doping impurities having a dopant type opposite to, that of said semiconductor substrate into said side portion of said active region outside of said first dielectric spacer in a self-aligned manner to form a deeper heavily-doped source/drain diffusion region;

performing a rapid-thermal-annealing process to redistribute implanted doping impurities with an extension portion of said shallow moderately-doped source/drain diffusion region formed under said graded gate-oxide layer;

performing a first-step self-aligned silicidation process for converting a major portion of said second conductive gate layer into a thicker silicide layer;

removing said thicker oxide layer and simultaneously etching said planarized field-oxides outside of said first dielectric spacer in a self-aligned manner to form a self-aligned source/drain contact hole over said deeper heavily-doped source/drain diffusion region; and

performing a second-step self-aligned silicidation process for forming a thin silicide layer over said deeper heavily-doped source/drain diffusion region and completely converting said second conductive gate layer into a thick silicide layer.

10. The method of claim 9, wherein said semiconductor substrate is a p-well or a p-type semiconductor substrate for fabricating an n-channel MOSFET or is an n-well or an n-type semiconductor substrate for fabricating a p-channel MOSFET.

11. The method of claim 9, wherein said conductive barrier-metal layer is preferably a refractory metal-nitride layer.

12. The method of claim 9, wherein said first conductive gate layer is made of amorphous-silicon or polycrystalline-silicon implanted with n-type dopants for fabricating said n-channel MOSFET or implanted with p-type dopants for fabricating said p-channel MOSFET.

13. The method of claim 9, wherein said gate structure can be a steep-gate structure or a taper-gate structure having a taper angle between about 45 degrees and 90 degrees.

14. The method of claim 9, wherein said second conductive gate layer is made of amorphous-silicon or polycrystalline-silicon.

15. The method of claim 9, wherein said second masking dielectric layer is preferably made of silicon-nitrides or oxynitrides and said first dielectric spacer is preferably made of silicon-nitrides.

16. The method of claim 9, wherein said thicker silicide layer or said thin silicide layer is preferably made of a refractory metal-silicide layer.