Silicon on III-V semiconductor bonding for monolithic optoelectronic integration

• US 6,455,398 B1
• Filed: 07/14/2000
• Issued: 09/24/2002
• Est. Priority Date: 07/16/1999
• Status: Expired due to Fees

• Current Assignee: Massachusetts Institute of Technology
• Original Assignee: Massachusetts Institute of Technology
• Inventors: London, Joanna M., Ahadian, Joseph F., Fonstad, Clifton G. Jr.
• Primary Examiner(s): Sherry, Michael
• Assistant Examiner(s): SARKAR, ASOK K
• Application Number:
  US09/616,456
• Time in Patent Office: 802 Days
• Field of Search: 438/455, 438/459
• US Class Current: 438/459
• CPC Class Codes: G02B 6/1245 Geodesic lenses
• CPC Class Codes: H01L 21/187 by direct bonding
• CPC Class Codes: H01L 21/2007 Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer H01L21/2011 takes precedence; bonding of semiconductor wafers to semiconductor wafers for junction formation H01L21/187
• CPC Class Codes: H01L 21/76251 using bonding techniques
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 21/76256 using silicon etch back techniques, e.g. BESOI, ELTRAN
• CPC Class Codes: H01L 21/8252 the substrate being a semiconductor, using III-V technology H01L21/8258 takes precedence
• CPC Class Codes: H01L 21/8258 the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213 , H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256
• CPC Class Codes: H01L 2221/68363 used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
• CPC Class Codes: H01L 27/0605 integrated circuits made of compound material, e.g. AIIIBV
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout

Abstract

In a method for bonding a silicon substrate to a III-V material substrate, a silicon substrate is contacted together with a III-V material substrate and the contacted substrates are annealed at a first temperature that is above ambient temperature, e.g., at a temperature of between about 150° C. and about 350° C. The silicon substrate is then thinned. This bonding process enables the fabrication of thick, strain-sensitive and defect-sensitive optoelectronic devices on the optimum substrate for such, namely, a thick III-V material substrate, while enabling the fabrication of silicon electronic devices in a thin silicon layer, resulting from the thinned Si substrate, that is sufficient for such fabrication but which has been thinned to eliminate thermally-induced stress in both the Si and III-V materials. The III-V material substrate thickness thereby provides the physical strength of the composite substrate structure, while the thinned silicon substrate minimizes stress in the composite structure.

Claims

1. A method for bonding a silicon substrate to a III-V material substrate, comprising the steps of:

contacting the silicon substrate together with the III-V material substrate;

annealing the contacted substrates at a first temperature above ambient temperature; and

thinning only the silicon substrate.

2. The method of claim 1 wherein annealing of the contacted substrates is carried out at a first temperature of between about 150°

C. and about 350°

C.

3. The method of claim 1 further comprising a last step of fabricating silicon electronic devices on the thinned silicon substrate.

4. The method of claim 3 further comprising a step of fabricating III-V electronic devices on the III-V material substrate after thinning of the silicon substrate.

5. The method of claim 3 further comprising a step of fabricating III-V material optical devices on the III-V material substrate after thinning of the silicon substrate.

6. The method of claim 5 wherein the step of fabricating III-V material optical devices comprises growing a heteroepitaxial layer on the III-V material substrate.

7. The method of claim 1 further comprising a step of fabricating silicon electronic devices on the silicon substrate before contacting the silicon substrate together with the III-V material substrate.

8. The method of claim 7 further comprising a step of fabricating III-V material electronic devices on the III-V material substrate before contacting the III-V material substrate together with the silicon substrate.

9. The method of claim 7 further comprising a step of fabricating III-V material optical devices on the III-V material substrate before contacting the III-V material substrate together with the silicon substrate.

10. The method of either of claims 4 or 8 further comprising a step of fabricating an electrical interconnection between silicon and III-V material electronic devices.

11. The method of claim 1 further comprising a first step of forming a dielectric layer on at least one of a silicon substrate surface and a III-V material substrate surface to be contacted together.

12. The method of claim 11 wherein forming a dielectric layer on at least one of a silicon substrate surface and a III-V material substrate surface to be contacted together comprises forming a dielectric layer on each of the silicon substrate surface and the III-V material substrate surface to be contacted together.

13. The method of claim 10 wherein the dielectric layer comprises an oxide layer.

14. The method of claim 11 wherein the dielectric layer comprises a nitride layer.

15. The method of claim 1 further comprising a first step of rendering hydrophilic a silicon substrate surface and a III-V material substrate surface to be contacted together.

16. The method of claim 1 wherein the III-V material substrate comprises a GaAs substrate.

17. The method of claim 1 wherein the III-V material substrate comprises an InP substrate.

18. The method of claim 1 wherein the step of thinning the silicon substrate comprises thinning the silicon substrate to a thickness of less than about 1 micron.

19. The method of claim 18 wherein the step of thinning the silicon substrate comprises thinning the silicon substrate to a thickness of less than about 5000 angstroms.

20. The method of claim 19 wherein the step of thinning the silicon substrate comprises thinning the silicon substrate to a thickness of less than about 2000 angstroms.

21. The method of claim 1 wherein the silicon substrate comprises a silicon-on-insulator (SOI) substrate.

22. The method of claim 1 wherein the silicon substrate comprises a separation-by-implantation-of-oxygen (SIMOX) substrate configuration.

23. The method of claim 1 wherein contacting the silicon substrate together with the III-V material substrate comprises applying pressure to the silicon substrate and the III-V material substrate as the silicon substrate and the III-V material substrate are contacted together.

24. The method of claim 1 further comprising a last step of annealing the III-V material substrate and the thinned silicon substrate at a second temperature that is greater than the first temperature.

25. The method of claim 24 wherein the second temperature is greater than about 200°

C.

26. The method of claim 25 wherein the second temperature is greater than about 350°

C.

27. The method of claim 1 further comprising a last step of annealing the III-V material substrate and the thinned silicon substrate at a second temperature at which further thermal processing of the substrates is to be carried out.