Semiconductor device having a fragment of a connection part provided on at least one lateral edge for mechanically connecting to adjacent semiconductor chips

• US 6,455,945 B1
• Filed: 03/18/1999
• Issued: 09/24/2002
• Est. Priority Date: 01/28/1994
• Status: Expired due to Fees

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Ishii, Masanori, Suzuki, Yoji, Suzuki, Hidetake
• Primary Examiner(s): Williams, Alexander O.
• Application Number:
  US09/270,843
• Time in Patent Office: 1,286 Days
• Field of Search: 257/706, 257/797, 257/723, 257/730, 257/724, 257/686, 257/685, 257/620, 257/777, 257/621
• US Class Current: 257/797
• CPC Class Codes: B05D 7/146 to metallic pipes or tubes processes for coating the interior of pipes B05D7/222
• CPC Class Codes: C08G 59/50 Amines
• CPC Class Codes: C08G 59/5006 aliphatic
• CPC Class Codes: C08G 59/54 Amino amides>
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2221/68359 used as a support during manufacture of interconnect decals or build up layers
• CPC Class Codes: H01L 2221/68368 used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
• CPC Class Codes: H01L 2223/54473 for use after dicing
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 24/96 the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01004 Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01024 Chromium [Cr]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01074 Tungsten [W]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/10158 : at the passive surface
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/10336 : Aluminium gallium arsenide [AlGaAs]
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/13064 : High Electron Mobility Transistor [HEMT, HFET [heterostructure FET], MODFET]
• CPC Class Codes: H01L 2924/30107 : Inductance

Abstract

A method for fabricating a semiconductor device includes the steps of forming a plurality of semiconductor chips on a semiconductor substrate, forming a connection part such that the connection part connects the semiconductor chips with other across an dicing line, bonding the semiconductor substrate upon a support substrate, removing the dicing region while maintaining the semiconductor chips in a state such that the semiconductor chips are bonded upon the support substrate, detaching the plurality of semiconductor chips from the support substrate while maintaining an alignment between the semiconductor chips, and separating the semiconductor chips from each other by eliminating the connection part.

Claims

1. A semiconductor device, comprising:

a semiconductor chip defined by lateral edges; and

a connection part provided at least on one of said lateral edges for maintaining an alignment with another semiconductor chip, said connection part being made of insulative material and having a width smaller than a size of said lateral edge on which said connection part is provided and is provided for mechanically connecting adjacent semiconductor chips with each other.

2. A semiconductor device as claimed in claim 1, wherein said lateral edge is formed with a plurality of said connection parts.

3. A semiconductor device having a plurality of layers, comprising:

a semiconductor chip defined by lateral edges; and

a connection part provided at least on one of said lateral edges for maintaining an alignment with another semiconductor chip, said connection part being made of at least one of said plurality of layers and having a width smaller than a size of said lateral edge on which said connection part is provided for mechanically connecting adjacent semiconductor chips with each other.

4. A semiconductor device as claimed in claim 3, wherein said lateral edge is formed with a plurality of said connection parts.