Low current redundancy anti-fuse method and apparatus

• US 6,456,149 B2
• Filed: 02/27/2001
• Issued: 09/24/2002
• Est. Priority Date: 10/03/1996
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Ho, Fan, Beigel, Kurt D., Cutter, Douglas J.
• Primary Examiner(s): Cunningham, Terry D.
• Assistant Examiner(s): Tra, Quan
• Application Number:
  US09/794,685
• Publication Number:
  US 20010007431A1
• Time in Patent Office: 574 Days
• Field of Search: 327/525, 327/526, 326/10, 326/38
• US Class Current: 327/525
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 29/785 with redundancy programming schemes
• CPC Class Codes: G11C 29/83 with reduced power consumption

Abstract

A programmable circuit includes a first node and provides a programmed signal based on the state of the first node. A first anti-fuse has a programmed state and an unprogrammed state and couples the first node to a first power supply when in the programmed state and decouples the first node from the first power supply when in the unprogrammed state. A second anti-fuse has a programmed state and an unprogrammed state and couples the first node to a second power supply when in the programmed state and decouples the first node from the second power supply when in the unprogrammed state. The state of the programmed signal can be used to replace a primary circuit element of an integrated circuit with a redundant circuit element.

Claims

1. An integrated circuit including a programmable circuit for providing a programmed signal, comprising:

a first node, wherein the state of the programmed signal is based on the state of the first node;

a first anti-fuse for selectively coupling the first node to a first power supply when in a programmed state and decoupling the first node from the first power supply when in an unprogrammed state; and

a second anti-fuse for selectively coupling the first node to a second power supply when in a programmed state and decoupling the first node from the second power supply when in an unprogrammed state;

wherein one terminal of the first anti-fuse is at a potential of the first power supply during normal operations of the integrated circuit; and

wherein one terminal of the second anti-fuse is at a potential of the second power supply during normal operations of the integrated circuit;

a compare circuit coupled to the first node and providing a match signal in response to the programmed signal, wherein the match signal, in a first state, disables a primary circuit and enables a redundant circuit.

2. The programmable circuit of claim 1, wherein the second power supply is a ground potential.

3. The programmable circuit of claim 1, wherein no long-L p-channel pull-up transistor is interposed between the first node and either power supply.

54. The integrated circuit of claim 1, wherein the match signal, in a second state, disables the redundant circuit.

4. An integrated circuit receiving n address bits and comprising:

primary circuit elements being selectable by binary values of the n address bits;

redundant circuit elements; and

match anti-fuse circuits corresponding to the redundant circuit elements, each match anti-fuse circuit comprising;

a plurality of programmable circuits, each being coupled to a first power supply and a second power supply and providing a programmed signal corresponding to one of the possible binary values of at least one of the n address bits, wherein each programmable circuit is responsive to a binary value of the at least one of the n address bits to activate the programmed signal when the binary value of the at least one of the n address bits corresponds to the programmed signal, each programmable circuit including;

a first node, wherein the state of the programmed signal is based on the state of the first node;

a first anti-fuse for selectively coupling the first node to a first power supply when in a programmed state and decoupling the first node from the first power supply when in an unprogrammed state; and

a second anti-fuse for selectively coupling the first node to a second power supply when in a programmed state and decoupling the first node from the second power supply when in an unprogrammed state;

wherein one terminal of the first anti-fuse is at a potential of the first power supply during normal operations of the integrated circuit; and

wherein one terminal of the second anti-fuse is at a potential of the second power supply during normal operations of the integrated circuit; and

a compare circuit coupled to the plurality of programmable circuits for activating a match signal in response to all of the programmed signals being active, wherein the activated match signal is used to disable a primary circuit element from being selected by a corresponding binary value of the n address bits and to enable the redundant circuit element to be selected by the corresponding binary value of the n address bits.

5. The integrated circuit of claim 4, wherein the first power supply is approximately Vcc.

6. The integrated circuit of claim 4, wherein the first power supply is approximately Vcc/2.

7. The integrated circuit of claim 4, wherein the second power supply is a ground potential.

8. An integrated circuit including a programmable circuit for providing a programmed signal, comprising:

a first node, wherein the state of the programmed signal is based on the state of the first node;

a first anti-fuse for selectively coupling the first node to a first power supply when in a programmed state and decoupling the first node from the first power supply when in an unprogrammed state; and

a second anti-fuse for selectively coupling the first node to a second power supply when in a programmed state and decoupling the first node from the second power supply when in an unprogrammed state;

wherein one terminal of the first anti-fuse is at a first potential of the first power supply during normal operations of the integrated circuit and is at a second potential during a programming operation of the integrated circuit; and

wherein one terminal of the second anti-fuse is at a third potential of the second power supply during normal operations of the integrated circuit;

a compare circuit coupled to the first node and providing a match signal in response to the programmed signal, wherein the match signal, in a first state, disables a primary circuit and enables a redundant circuit.

9. The programmable circuit of claim 8, wherein the third potential of the second power supply is a ground potential.

10. The programmable circuit of claim 8, wherein no long-L p-channel pull-up transistor is interposed between the first node and either power supply.

11. The programmable circuit of claim 8, wherein the first power supply is Vcc.

12. The programmable circuit of claim 8, wherein the first power supply is DVC2.

13. The programmable circuit of claim 8, wherein the second potential exceeds a breakdown voltage of the first antifuse.

14. The programmable circuit of claim 8, wherein the second potential exceeds 10 Volts.

55. The integrated circuit of claim 8, wherein the match signal, in a second state, disables the redundant circuit.

15. An integrated circuit including a programmable circuit for providing a programmed signal, comprising:

a first node, wherein the state of the programmed signal is based on the state of the first node;

a first anti-fuse for selectively coupling the first node to a first power supply when in a programmed state and decoupling the first node from the first power supply when in an unprogrammed state; and

a second anti-fuse for selectively coupling the first node to a second power supply when in a programmed state and decoupling the first node from the second power supply when in an unprogrammed state;

wherein one terminal of the first anti-fuse is at a first potential of the first power supply during normal operations of the integrated circuit; and

wherein one terminal of the second anti-fuse is at a second potential of the second power supply during normal operations of the integrated circuit and is at a third potential during a programming operation of the integrated circuit;

a compare circuit coupled to the first node and providing a match signal in response to the programmed signal, wherein the match signal, in a first state, disables a primary circuit and enables a redundant circuit.

16. The programmable circuit of claim 15, wherein the second potential of the second power supply is a ground potential.

17. The programmable circuit of claim 15, wherein no long-L p-channel pull-up transistor is interposed between the first node and either power supply.

18. The programmable circuit of claim 15, wherein the first potential of the first power supply is Vcc.

19. The programmable circuit of claim 15, wherein the first potential of the first power supply is DVC2.

20. The programmable circuit of claim 15, wherein the third potential exceeds a breakdown voltage of the second anti-fuse.

21. The programmable circuit of claim 15, wherein the third potential exceeds 10 Volts.

56. The integrated circuit of claim 15, wherein the match signal, in a second state, disables the redundant circuit.

22. An integrated circuit including a programmable circuit for providing a programmed signal, comprising:

a first node, wherein the state of the programmed signal is based on the state of the first node;

a first anti-fuse for selectively coupling the first node to a first power supply when in a programmed state and decoupling the first node from the first power supply when in an unprogrammed state; and

a second anti-fuse for selectively coupling the first node to a second power supply when in a programmed state and decoupling the first node from the second power supply when in an unprogrammed state;

wherein one terminal of the first anti-fuse is always at a first potential of the first power supply during normal operations of the integrated circuit and is at a second potential during a programming operation of the integrated circuit; and

wherein one terminal of the second anti-fuse is always at a third potential of the second power supply during normal operations of the integrated circuit and is at a fourth potential during a programming operation of the integrated circuit;

a compare circuit coupled to the first node and providing a match signal in response to the programmed signal, wherein the match signal, in a first state, disables a primary circuit and enables a redundant circuit.

23. The programmable circuit of claim 22, wherein the third potential is a ground potential.

24. The programmable circuit of claim 22, wherein no long-L p-channel pull-up transistor is interposed between the first node and either power supply.

25. The programmable circuit of claim 22, wherein the first potential is Vcc.

26. The programmable circuit of claim 22, wherein the first potential is DVC2.

27. The programmable circuit of claim 22, wherein the fourth potential exceeds a breakdown voltage of the second anti-fuse.

28. The programmable circuit of claim 22, wherein the fourth potential exceeds 10 Volts.

29. The programmable circuit of claim 22, wherein the second potential exceeds a breakdown voltage of the first anti-fuse.

30. The programmable circuit of claim 22, wherein the second potential exceeds 10 Volts.

57. The integrated circuit of claim 22, wherein the match signal, in a second state, disables the redundant circuit.

31. An integrated circuit receiving n address bits and comprising:

primary circuit elements being selectable by binary values of the n address bits;

redundant circuit elements; and

match anti-fuse circuits corresponding to the redundant circuit elements, each match anti-fuse circuit comprising;

a plurality of programmable circuits, each being coupled to a first power supply and a second power supply and providing a programmed signal corresponding to one of the possible binary values of at least one of the n address bits, wherein each programmable circuit is responsive to a binary value of the at least one of the n address bits to activate the programmed signal when the binary value of the at least one of the n address bits corresponds to the programmed signal, each programmable circuit including;

a first node, wherein the state of the programmed signal is based on the state of the first node;

a first anti-fuse for selectively coupling the first node to a first power supply when in a programmed state and decoupling the first node from the first power supply when in an unprogrammed state; and

a second anti-fuse for selectively coupling the first node to a second power supply when in a programmed state and decoupling the first node from the second power supply when in an unprogrammed state;

wherein one terminal of the first anti-fuse is at a first potential of the first power supply during normal operations of the integrated circuit and is at a second potential during a programming operation of the integrated circuit; and

wherein one terminal of the second anti-fuse is at a third potential of the second power supply during normal operations of the integrated circuit; and

a compare circuit coupled to the plurality of programmable circuits for activating a match signal in response to all of the programmed signals being active, wherein the activated match signal is used to disable a primary circuit element from being selected by a corresponding binary value of the n address bits and to enable the redundant circuit element to be selected by the corresponding binary value of the n address bits.

32. The integrated circuit of claim 31, wherein the third potential is a ground potential.

33. The integrated circuit of claim 31, wherein no long-L p-channel pull-up transistor is interposed between the first node and either power supply.

34. The integrated circuit of claim 31, wherein the first potential is Vcc.

35. The integrated circuit of claim 31, wherein the first potential is DVC2.

36. The integrated circuit of claim 31, wherein the second potential exceeds a breakdown voltage of the first anti-fuse.

37. The integrated circuit of claim 31, wherein the second potential exceeds 10 Volts.

38. An integrated circuit receiving n address bits and comprising:

primary circuit elements being selectable by binary values of the n address bits;

redundant circuit elements; and

match anti-fuse circuits corresponding to the redundant circuit elements, each match anti-fuse circuit comprising;

a plurality of programmable circuits, each being coupled to a first power supply and a second power supply and providing a programmed signal corresponding to one of the possible binary values of at least one of the n address bits, wherein each programmable circuit is responsive to a binary value of the at least one of the n address bits to activate the programmed signal when the binary value of the at least one of the n address bits corresponds to the programmed signal, each programmable circuit including;

a first node, wherein the state of the programmed signal is based on the state of the first node;

a first anti-fuse for selectively coupling the first node to a first power supply when in a programmed state and decoupling the first node from the first power supply when in an unprogrammed state; and

a second anti-fuse for selectively coupling the first node to a second power supply when in a programmed state and decoupling the first node from the second power supply when in an unprogrammed state;

wherein one terminal of the first anti-fuse is at a first potential of the first power supply during normal operations of the integrated circuit; and

wherein one terminal of the second anti-fuse is at a second potential of the second power supply during normal operations of the integrated circuit and is at a third potential during a programming operation of the integrated circuit; and

a compare circuit coupled to the plurality of programmable circuits for activating a match signal in response to all of the programmed signals being active, wherein the activated match signal is used to disable a primary circuit element from being selected by a corresponding binary value of the n address bits and to enable the redundant circuit element to be selected by the corresponding binary value of the n address bits.

39. The integrated circuit of claim 38, wherein the second potential is a ground potential.

40. The integrated circuit of claim 38, wherein no long-L p-channel pull-up transistor is interposed between the first node and either power supply.

41. The integrated circuit of claim 38, wherein the first potential is Vcc.

42. The integrated circuit of claim 38, wherein the first potential is DVC2.

43. The integrated circuit of claim 38, wherein the third potential exceeds a breakdown voltage of the second anti-fuse.

44. The integrated circuit of claim 38, wherein the second potential exceeds 10 Volts.

45. An integrated circuit receiving n address bits and comprising:

primary circuit elements being selectable by binary values of the n address bits;

redundant circuit elements; and

match anti-fuse circuits corresponding to the redundant circuit elements, each match anti-fuse circuit comprising;

a plurality of programmable circuits, each being coupled to a first power supply and a second power supply and providing a programmed signal corresponding to one of the possible binary values of at least one of the n address bits, wherein each programmable circuit is responsive to a binary value of the at least one of the n address bits to activate the programmed signal when the binary value of the at least one of the n address bits corresponds to the programmed signal, each programmable circuit including;

a first node, wherein the state of the programmed signal is based on the state of the first node;

a first anti-fuse for selectively coupling the first node to a first power supply when in a programmed state and decoupling the first node from the first power supply when in an unprogrammed state; and

a second anti-fuse for selectively coupling the first node to a second power supply when in a programmed state and decoupling the first node from the second power supply when in an unprogrammed state;

wherein one terminal of the first anti-fuse is at a first potential of the first power supply during normal operations of the integrated circuit and is at a second potential during a programming operation of the integrated circuit; and

wherein one terminal of the second anti-fuse is at a third potential of the second power supply during normal operations of the integrated circuit and is at a fourth potential during a programming operation of the integrated circuit; and

a compare circuit coupled to the plurality of programmable circuits for activating a match signal in response to all of the programmed signals being active, wherein the activated match signal is used to disable a primary circuit element from being selected by a corresponding binary value of the n address bits and to enable the redundant circuit element to be selected by the corresponding binary value of the n address bits.

46. The integrated circuit of claim 45, wherein the third potential is a ground potential.

47. The integrated circuit of claim 45, wherein no long-L p-channel pull-up transistor is interposed between the first node and either power supply.

48. The integrated circuit of claim 45, wherein the first potential is Vcc.

49. The integrated circuit of claim 45, wherein the first potential is DVC2.

50. The integrated circuit of claim 45, wherein the second potential exceeds a breakdown voltage of the first anti-fuse.

51. The integrated circuit of claim 45, wherein the second potential exceeds 10 Volts.

52. The integrated circuit of claim 45, wherein the fourth potential exceeds a breakdown voltage of the second anti-fuse.

53. The integrated circuit of claim 45, wherein the fourth potential exceeds 10 Volts.

58. A memory device in an integrated circuit, comprising:

primary circuit elements being selectable by binary values of address bits;

redundant circuit elements; and

match anti-fuse circuits, each match anti-fuse circuit comprising;

a plurality of programmable circuits, each being coupled to a first power supply and a second power supply and providing a programmed signal corresponding to one of the possible binary values of at least one of the address bits, wherein each programmable circuit is responsive to a binary value of the at least one of the address bits to activate the programmed signal when the binary value of the at least one of the address bits corresponds to the programmed signal, each programmable circuit including;

a first node, wherein the state of the programmed signal is based on the state of the first node;

a first anti-fuse for selectively coupling the first node to a first power supply when in a programmed state and decoupling the first node from the first power supply when in an unprogrammed state; and

a second anti-fuse for selectively coupling the first node to a second power supply when in a programmed state and decoupling the first node from the second power supply when in an unprogrammed state;

wherein one terminal of the first anti-fuse is at a potential of the first power supply during normal operations of the integrated circuit; and

wherein one terminal of the second anti-fuse is at a potential of the second power supply during normal operations of the integrated circuit; and

a compare circuit coupled to the plurality of programmable circuits for activating a match signal in response to all of the programmed signals being active, wherein the activated match signal is used to disable a primary circuit element from being selected by a corresponding binary value of the address bits and to enable the redundant circuit element to be selected by the corresponding binary value of the address bits.

59. The memory device of claim 58, wherein the matching circuit elements correspond to the redundant circuit elements.

60. The memory device of claim 58, wherein the primary circuit elements are adapted to store digital data.

61. The memory device of claim 58, wherein the primary circuit elements are part of a DRAM or SRAM.