Cyclic redundancy calculation circuitry for use in medical devices and methods regarding same

• US 6,456,875 B1
• Filed: 10/12/1999
• Issued: 09/24/2002
• Est. Priority Date: 10/12/1999
• Status: Expired due to Term

• Current Assignee: Medtronic Incorporated (Medtronic Plc)
• Original Assignee: Medtronic Incorporated (Medtronic Plc)
• Inventors: Walsh, Kevin K., Hocken, Robert W., Wilkinson, Jeffrey D.
• Primary Examiner(s): Schaetzle, Kennedy
• Application Number:
  US09/416,667
• Time in Patent Office: 1,078 Days
• Field of Search: 714/781, 714/799, 714/807, 714/758, 607/31, 607/32, 607/2, 607/30, 607/60, 128/901, 128/903, 128/904
• US Class Current: 607/2
• CPC Class Codes: H03M 13/091 Parallel or block-wise CRC computation

Abstract

Cyclic redundancy calculations are provided by operating on a data stream, e.g., a data stream in an implantable medical device, to perform a polynomial division thereon using one of a first cyclic redundancy code generator polynomial and a second cyclic redundancy code generator polynomial. The first cyclic redundancy code generator polynomial is a higher order polynomial than the second cyclic redundancy code generator polynomial and contains all terms of the second cyclic redundancy code generator polynomial. The polynomial division may be implemented using linear feedback shift register circuitry and circuitry to select between the use of the first or second cyclic redundancy code generator polynomial.

Claims

1. A method for providing a cyclic redundancy calculation in a medical device, the method comprising the steps of:

providing a medical device having a housing;

providing one or more circuits to implement at least a first and second cyclic redundancy code generator polynomial, wherein the first cyclic redundancy code generator polynomial is a polynomial expressed as a first set of terms and is of a higher order than the second cyclic redundancy code generator polynomial which is expressed as a second set of terms, and further wherein the first set of terms of the first cyclic redundancy code generator polynomial contains all the second set of terms of the second cyclic redundancy code generator polynomial; and

enclosing the one or more circuits within the housing of the medical device.

2. The method of claim 1, wherein the method further includes selecting between use of the first and second cyclic redundancy code generator polynomial to perform a polynomial division for a data stream input to the one or more circuits resulting in a cyclic redundancy code.

3. The method of claim 2, wherein providing one or more circuits to implement at least a first and second cyclic redundancy code generator polynomial includes providing a first linear feedback shift register circuit and a second linear feedback shift register circuit, and further wherein selecting between use of the first and second cyclic redundancy code generator polynomial to perform a polynomial division includes using both the first linear feedback shift register circuit and the second linear feedback shift register circuit to perform a polynomial division using the first cyclic redundancy code generator polynomial and using one of the first and second linear feedback shift register circuits to perform a polynomial division using the second cyclic redundancy code generator polynomial.

4. The method of claim 3, wherein the first and second linear feedback shift register circuits are implemented using serially connected latches and XOR gates.

5. The method of claim 3, wherein selection of the first cyclic redundancy code generator polynomial results in a 16-bit cyclic redundancy code and selection of the second cyclic redundancy code generator polynomial results in an 8-bit cyclic redundancy code.

6. The method of claim 2, wherein the data stream includes data received from a memory device of the medical device.

7. The method of claim 6, wherein the data stream includes data received from a non-volatile memory device of the medical device.

8. The method of claim 2, wherein the data stream includes data communicated between a transmitter and a receiver.

9. The method of claim 1, wherein the medical device includes an implantable device selected from one of a pacemaker, a defibrillator, a pacemaker/cardioverter/defibrillator, a cardioverter/defibrillator, a brain stimulator, a neurostimulator, a muscle stimulator, a gastric stimulator, an implantable monitor, a hemodynamic monitor, and a drug pump.

10. A method for use in performing a cyclic redundancy calculation in a medical device, the method comprising the steps of:

receiving a data stream representative of information associated with the medical device; and

operating on the data stream to perform a polynomial division using one of at least a first cyclic redundancy code generator polynomial and a second cyclic redundancy code generator polynomial to generate a cyclic redundancy code, wherein the first cyclic redundancy code generator polynomial is a higher order polynomial than the second cyclic redundancy code generator polynomial and contains all terms of the second cyclic redundancy code generator polynomial.

11. The method of claim 10, wherein operating on the data stream to perform a polynomial division includes:

providing a first linear feedback shift register circuit and a second linear feedback shift register circuit; and

selecting between use of the first and second cyclic redundancy code generator polynomial to perform a polynomial division, wherein both the first linear feedback shift register circuit and the second linear feedback shift register circuit are used to perform a polynomial division when use of the first cyclic redundancy code generator polynomial is selected, and further wherein one of the first and second linear feedback shift register circuits is used to perform a polynomial division when use of is the second cyclic redundancy code generator polynomial is selected.

12. The method of claim 11, wherein the first and second linear feedback shift register circuits are implemented using serially connected latches and XOR gates.

13. The method of claim 10, wherein the polynomial division is used to encode the data stream.

14. The method of claim 10, wherein the data stream includes data received from a memory device of the medical device.

15. The method of claim 10, wherein the polynomial division is used to decode the data stream.

16. The method of claim 10, wherein the medical device is an implantable device selected from one of a pacemaker, a defibrillator, a pacemaker/cardioverter/defibrillator, a cardioverter/defibrillator, a brain stimulator, a neurostimulator, a muscle stimulator, a gastric stimulator, an implantable monitor, a hemodynamic monitor, and a drug pump.

17. A medical device comprising:

a housing;

one or more circuits enclosed in the housing, wherein the one or more circuits are operable to receive a data stream representative of information associated with the medical device, and further wherein the one or more circuits are operable on the data stream to perform a polynomial division using one of at least a first cyclic redundancy code generator polynomial and a second cyclic redundancy code generator polynomial to generate a cyclic redundancy code, wherein the first cyclic redundancy code generator polynomial is a higher order polynomial than the second cyclic redundancy code generator polynomial and contains all terms of the second cyclic redundancy code generator polynomial .

18. The device of claim 17, wherein the one or more circuits include:

a first linear feedback shift register circuit and a second linear feedback shift register circuit configured to perform the polynomial division; and

a multiplexer for use in selecting between use of the first and second cyclic redundancy code generator polynomial to perform the polynomial division.

19. The device of claim 18, wherein both the first linear feedback shift register circuit and the second linear feedback shift register circuit are used to perform a polynomial division using the first cyclic redundancy code generator polynomial and wherein one of the first and second linear feedback shift register circuits is used to perform a polynomial division using the second cyclic redundancy code generator polynomial.

20. The device of claim 19, wherein the first and second linear feedback shift register circuits are implemented using serially connected latches and XOR gates.

21. The device of claim 19, wherein the polynomial division using the first cyclic redundancy code generator polynomial results in a 16-bit cyclic redundancy code and the polynomial division using the second cyclic redundancy code generator polynomial results in an 8-bit cyclic redundancy code.

22. The device of claim 17 wherein the polynomial division is used for encoding the data stream.

23. The device of claim 17, wherein the data stream includes data received from a memory device of the medical device.

24. The device of claim 17, wherein the polynomial division is used for decoding the data stream.

25. The method of claim 17, wherein the medical device is an implantable device selected from one of a pacemaker, a defibrillator, a pacemaker/cardioverter/defibrillator, a cardioverter/defibrillator, a brain stimulator, a neurostimulator, a muscle stimulator, a gastric stimulator, an implantable monitor, a hemodynamic monitor, and a drug pump.

26. A method for use in performing a cyclic redundancy calculations, the method comprising:

providing a data stream; and

operating on the data stream to perform a polynomial division thereon using one of at least a first cyclic redundancy code generator polynomial and a second cyclic redundancy code generator polynomial to generate a cyclic redundancy code, wherein the first cyclic redundancy code generator polynomial is a higher order polynomial than the second cyclic redundancy code generator polynomial and contains all terms of the second cyclic redundancy code generator polynomial.

27. The method of claim 26, wherein operating on the data stream to perform a polynomial division includes:

providing a first linear feedback shift register circuit and a second linear feedback shift register circuit; and

selecting between use of the first and second cyclic redundancy code generator polynomial to perform the polynomial division, wherein both the first linear feedback shift register circuit and the second linear feedback shift register circuit are used to perform a polynomial division when use of the first cyclic redundancy code generator polynomial is selected, and further wherein one of the first and second linear feedback shift register circuits is used to perform a polynomial division when use of the second cyclic redundancy code generator polynomial is selected.

28. The method of claim 27, wherein the first and second linear feedback shift register circuits are each implemented using serially connected latches and XOR gates.

29. The method of claim 28, wherein operating on the data stream to perform a polynomial division thereon using the first cyclic redundancy code generator polynomial includes:

clocking a block of data of the data stream through the serially connected first and second linear feedback shift register circuits; and

providing the cyclic redundancy code from both the first and second linear feedback shift register circuits after the block of data is clocked into the serially connected first and second linear feedback shift register circuits.

30. The method of claim 28, wherein operating on the data stream to perform a polynomial division thereon using the second cyclic redundancy code generator polynomial includes:

clocking a block of data of the data stream through at least the first linear feedback shift register circuit; and

providing the cyclic redundancy code from the first linear feedback shift register circuit of the serially connected first and second linear feedback shift register circuits after the block of data is clocked into at least the first linear feedback shift register circuit.

31. A method for performing a cyclic redundancy calculation, the method comprising:

providing one or more blocks of data;

operating on a first block of data to perform a polynomial division thereon using a first cyclic redundancy code generator polynomial to generate a cyclic redundancy code for the block of data; and

operating on a second block of data to perform a polynomial is division thereon using a second cyclic redundancy code generator polynomial to generate a cyclic redundancy code, wherein operating on the second block of data to perform the polynomial division thereon using the second generator polynomial is performed using a portion of circuitry used to operate on the first block of data to perform the polynomial division thereon using a first cyclic redundancy code generator polynomial.

32. The method of claim 31, wherein the first cyclic redundancy code generator polynomial is a polynomial expressed as a first set of terms and is of a higher order than the second cyclic redundancy code generator polynomial which is expressed as a second set of terms, and further wherein the first set of terms of the first cyclic redundancy code generator polynomial contains all the second set of terms of the second cyclic redundancy code generator.

33. The method of claim 31, wherein the method further includes selecting between use of the first and second cyclic redundancy code generator polynomial to perform a polynomial division for a data block.

34. The method of claim 31, wherein the circuitry includes a first linear feedback shift register circuit operatively connected to a second linear feedback shift register circuit, and further wherein both the first linear feedback shift register circuit and the second linear feedback shift register circuit are used to perform a polynomial division using the first cyclic redundancy code generator polynomial and wherein one of the first and second linear feedback shift register circuits is used to perform a polynomial division using the second cyclic redundancy code generator polynomial.

35. The method of claim 34, wherein the first and second linear feedback shift register circuits are implemented using serially connected latches and XOR gates.

36. The method of claim 31, wherein polynomial division using the first cyclic redundancy code generator polynomial results in a 16-bit cyclic redundancy code and polynomial division using the second cyclic redundancy code generator polynomial results in an 8-bit cyclic redundancy code.

37. A cyclic redundancy code calculation apparatus comprising one or more circuits to receive one or more data blocks, and further wherein the one or more circuits are operable on the one or more data blocks to perform a polynomial division using one of at least a first cyclic redundancy code generator polynomial and a second cyclic redundancy code generator polynomial to generate a cyclic redundancy code, wherein the first cyclic redundancy code generator polynomial is a higher order polynomial than the second cyclic redundancy code generator polynomial and contains all terms of the second cyclic redundancy code generator.

38. The apparatus of claim 37, wherein the one or more circuits include:

a first linear feedback shift register circuit operatively connected to a second linear feedback shift register circuit to perform the polynomial division; and

a multiplexer for use in selecting between use of the first and second cyclic redundancy code generator polynomial to perform the polynomial division.

39. The apparatus of claim 38, wherein both the first linear feedback shift register circuit and the second linear feedback shift register circuit are used to perform a polynomial division using the first cyclic redundancy code generator polynomial and wherein one of the first and second linear feedback shift register circuits is used to perform a polynomial division using the second cyclic redundancy code generator polynomial.

40. The apparatus of claim 39, wherein the first and second linear feedback shift register circuits include serially connected latches and XOR gates.

41. The apparatus of claim 38, wherein selection of the first cyclic redundancy code generator polynomial results in a 16-bit cyclic redundancy code and selection of the second cyclic redundancy code generator polynomial results in an 8-bit cyclic redundancy code.

42. A cyclic redundancy code calculation apparatus comprising:

a first linear feedback shift register circuit operable to receive data;

a second linear feedback shift register circuit serially connected to the first linear feedback shift register circuit, wherein the first linear feedback shift register circuit is configured with the second linear feedback shift register circuit for performing a polynomial division on the data using a first cyclic redundancy code generator polynomial, and further wherein the first linear feedback shift register circuit is configured for use in performing a polynomial division on the data using a second cyclic redundancy code generator polynomial.

43. The apparatus of claim 42, wherein the first cyclic redundancy code generator polynomial is a higher order polynomial than the second cyclic redundancy code generator polynomial and contains all terms of the second cyclic redundancy code generator polynomial.

44. The apparatus of claim 42, wherein the apparatus further includes a multiplexer for use in selecting between use of the first and second cyclic redundancy code generator polynomial to perform the polynomial division.

45. The apparatus of claim 42, wherein the first and second linear feedback shift register circuits include serially connected latches and XOR gates.

46. The apparatus of claim 42, wherein polynomial division using the first cyclic redundancy code generator polynomial results in a 16-bit cyclic redundancy code and wherein polynomial division using the second cyclic redundancy code generator polynomial results in an 8-bit cyclic redundancy code.