System and method for crash handling on redundant systems

• US 6,457,138 B1
• Filed: 04/19/1999
• Issued: 09/24/2002
• Est. Priority Date: 04/19/1999
• Status: Active Grant

• Current Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Original Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Inventors: May, William, Moberg, Kenneth, Lesser, Ofrit
• Primary Examiner(s): Iqbal, Nadeem
• Application Number:
  US09/294,452
• Time in Patent Office: 1,254 Days
• Field of Search: 714/1, 714/2, 714/6, 714/8, 714/10, 714/11, 714/13, 714/25, 714/31, 714/35, 714/39, 714/47, 714/7
• US Class Current: 714/1
• CPC Class Codes: G06F 11/2023 Failover techniques
• CPC Class Codes: G06F 11/2035 without idle spare hardware

Abstract

The present invention relates to providing processor redundancy in a system such as a router. According to an embodiment of the present invention, when a primary processor is about to crash in a system having two or more processors, the imminent crash is identified prior to the occurrence of the actual crash. The primary processor sends a message to the secondary processor to indicate that it is crashing. The primary also sets a timer to determine a period of time to wait prior to crashing. When the secondary processor receives the message from the primary processor, the secondary processor becomes the new primary processor. The new primary processor then sends an acknowledgement to the old primary processor. The old primary processor crashes and reboots as the new secondary processor.

Claims

1. A method for handling a crash on a redundant processor system, comprising:

determining that a primary processor is about to crash;

suspending the crash; and

sending a message from the primary processor to a secondary processor indicating that the primary processor is about to crash.

2. The method of claim 1, wherein determining that the primary processor is about to crash occurs when a hardware exception has been received.

3. The method of claim 1, wherein determining that the primary processor is about to crash occurs when a crash dump routine has been called.

4. The method of claim 1, wherein the message is sent via an out of band transmit routine.

5. The method of claim 1, further comprising setting a timer.

6. The method of claim 1, further comprising resuming the crash after a predetermined period of time.

7. The method of claim 1, further comprising switching the secondary processor to a second primary processor.

8. The method of claim 1, further comprising receiving an acknowledgement from the secondary processor.

9. The method of claim 1, further comprising resuming the crash after receiving an acknowledgement from the secondary processor.

10. The method of claim 1, further comprising booting the primary processor as a second secondary processor.

11. A method of handling a crash on a redundant processor system, comprising:

determining that a secondary processor is about to crash;

sending a message from the secondary processor to a primary processor indicating that the secondary processor is about to crash;

sending crash information; and

booting the secondary processor.

12. The method of claim 11, wherein determining that the secondary processor is about to crash occurs when a hardware exception has been received.

13. The method of claim 11, wherein determining that the secondary processor is about to crash occurs when a crash dump routine has been called.

14. The method of claim 11, wherein the message is sent via an out of band transmit routine.

15. A system for handling a crash on a redundant processor, comprising:

a primary processor configured to identify a crash, wherein the identification is performed prior to the occurrence of the crash;

the primary processor also configured to suspend the crash and send a message to a secondary processor indicating that the primary processor is about to crash; and

a memory coupled to the primary processor, wherein the memory is configured to provide instructions to the primary processor.

16. The system of claim 15, wherein determining that the primary processor is about to crash occurs when a hardware exception has been received.

17. The system of claim 15, wherein determining that the primary processor is about to crash occurs when a crash dump routine has been called.

18. The system of claim 15, further comprising resuming the crash after receiving an acknowledgement from the secondary processor.

19. A computer program product for handling a crash on a redundant processor system, comprising:

computer code determining that a primary processor is about to crash;

computer code suspending the crash;

computer code sending a message from the primary processor to a secondary processor indicating that the primary processor is about to crash; and

a computer readable medium that stores the computer codes.

20. The computer program product of claim 19, wherein the computer readable medium is selected from the group consisting of CD-ROM, floppy disk, tape, flash memory, system memory, hard drive, and data signal embodied in a carrier wave.