Functional timing analysis for characterization of virtual component blocks

• US 6,457,159 B1
• Filed: 12/28/1999
• Issued: 09/24/2002
• Est. Priority Date: 12/29/1998
• Status: Expired due to Term

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Yalcin, Hakan, Palmero, Robert J., Mortazavi, Mohammad S., Bamji, Cyrus, Sakallah, Karem A.
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Dinh, Paul
• Application Number:
  US09/477,710
• Time in Patent Office: 1,001 Days
• Field of Search: 716/1, 716/2, 716/3, 716/4, 716/5, 716/6, 716/7, 716/8, 716/9, 716/10, 716/11, 716/18, 703/19, 703/14, 703/15, 703/16
• US Class Current: 716/104
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

A system and method for performing a timing analysis on virtual component blocks or other circuit models is provided wherein functional information obtained from the circuit'"'"'s control inputs and their useful combinations is used to improve accuracy. The control inputs and data inputs for a circuit block are identified. Each functionally meaningful or useful control input combination is applied to the circuit block, and the topological delay for the data inputs are determined only along the paths that are not blocked by the control inputs. The delays along paths that are blocked are ignored. The analysis is further augmented by determining the topological delay for all paths originating at control inputs, without regard to blocking of paths, so as to reduce the chance for possible underestimation of delays from the data inputs. A final timing model may include the combination of maximum delays along data paths for each combination of control inputs, and maximum delays along paths originating from each of the control inputs. The delay analysis may account for different input slews and load capacitances, and the results may be expressed in tabular or matrix form. A useful technique for condensing time delay information (whether scalar or tabular in form) is also provided, to simplify timing characterization of a virtual component block or circuit model. Delay tables or matrixes that are “close” (i.e., within a specified tolerance) may be combined into a single table or matrix.

Claims

1. A method of analyzing timing in a circuit model, said circuit model including a plurality of inputs and one or more outputs, said plurality of inputs divided into a set of one or more data inputs and a set of one or more control inputs, said method comprising the steps of:

(a) identifying a set of modes, each of said modes corresponding to a unique combination of control input values for the circuit model;

(b) applying the combination of control input values for one of said modes to the circuit model;

(c) for each data input, calculating a maximum delay for each input/output path not passing through a blocked circuit node for the applied combination of control input values;

(d) recording the maximum delay for each input/output path not passing through a blocked circuit node for the applied combination of control input values; and

(e) repeating steps (b) through (d) for each of the remaining combinations of control inputs within the set of control inputs.

2. The method of claim 1, further comprising the step of calculating a maximum control input delay over a path from each control input in said set of control inputs to said one or more outputs.

3. The method of claim 1, wherein step (c) comprises the step of calculating a maximum delay for each input/output path for each of a plurality of input slews and output load capacitances, and wherein step (d) comprises the step of recording in a delay table the maximum delay for each input/output path for each of said plurality of input slews and output load capacitances.

4. The method of claim 3, wherein a plurality of delay tables are generated by recording the maximum delay for each input/output path for each of said plurality of input slews and output load capacitances, said method further comprising the step of merging at least two of said delay tables to form a new delay table.

5. The method of claim 4, wherein said step of merging at least two of said delay tables to form said new delay table comprises the steps of ordering said delay tables in ascending or descending order based upon an aggregate sum of delay values in each delay table, evaluating the nearness of said delay tables to one another based upon a specified tolerance, and merging two adjacent delay tables if each element of a first one of said two adjacent delay tables is within said specified tolerance of an element of a second one of said two adjacent delay tables in a same relative position.

6. A method of analyzing timing in a circuit model, said circuit model including a plurality of inputs, one or more outputs, and a plurality of input/output paths between said plurality of inputs and said one or more outputs, said method comprising the steps of:

(a) dividing a plurality of inputs for the circuit model into a set of one or more data inputs and a set of one or more control inputs;

(b) identifying a set of modes, each of said modes corresponding to a unique combination of control input values for the circuit model;

(c) applying the combination of control input values for one of said modes to the circuit model;

(d) for each data input, calculating a maximum delay for each input/output path not passing through a blocked circuit node for the applied combination of control input values;

(e) recording the maximum delay for each input/output path not passing through a blocked circuit node for the applied combination of control input values; and

(f) repeating steps (c) through (e) for each of the remaining combinations of control inputs within the set of control inputs.

7. The method of claim 6, further comprising the step of calculating a maximum control input delay over a path from each control input in said set of control inputs to said one or more outputs.

8. The method of claim 6, wherein step (e) comprises the step of calculating a maximum delay for each input/output path for each of a plurality of input slews and output load capacitances, and wherein step (e) comprises the step of recording in a delay table the maximum delay for each input/output path for each of said plurality of input slews and output load capacitances.

9. A computer readable medium having stored therein one or more sequences of instructions for analyzing timing in a circuit model, said circuit model including a plurality of inputs, one or more outputs, and a plurality of input/output paths between said plurality of inputs and said one or more outputs, said one or more sequences of instructions causing one or more processors to perform a plurality of acts, said acts comprising:

(a) receiving a circuit model;

(b) receiving a set of modes each corresponding to a unique combination of control input values for the circuit model;

(c) applying the combination of control input values for one of said modes to the circuit model;

(d) for each data input, calculating a maximum delay for each input/output path not passing through a blocked circuit node for the applied combination of control input values;

(e) recording, in a data structure, the maximum delay for each input/output path not passing through a blocked circuit node for the applied combination of control input values; and

(f) repeating steps (c) through (d) for each of the remaining combinations of control inputs within the set of control inputs.

10. The computer readable medium of claim 9, wherein said acts further comprise calculating a maximum control input delay over a path from each control input in said set of control inputs to said one or more outputs.

11. The computer readable medium of claim 9, wherein the act of calculating said maximum delay for each input/output path not passing through a blocked circuit node for the applied combination of control input values includes the act of calculating a maximum delay for each input/output path for each of a plurality of input slews and output load capacitances, and wherein the act of recording, in said data structure, the maximum delay for each input/output path not passing through a blocked circuit node for the applied combination of control input values includes the act of recording in a delay table the maximum delay for each input/output path for each of said plurality of input slews and output load capacitances.

12. The computer readable medium of claim 9, wherein the act of calculating said maximum delay for each input/output path not passing through a blocked circuit node for the applied combination of control input values is carried out using a logic simulator.