Method of fabricating micromachined structures and devices formed therefrom

• US 6,458,615 B1
• Filed: 09/30/1999
• Issued: 10/01/2002
• Est. Priority Date: 09/30/1999
• Status: Expired due to Term

• Current Assignee: Carnegie Mellon University
• Original Assignee: Carnegie Mellon University
• Inventors: Zhu, Xu, Fedder, Gary K.
• Primary Examiner(s): Whitehead, Jr., Carl
• Assistant Examiner(s): BROPHY, JAMIE LYNN
• Application Number:
  US09/409,570
• Time in Patent Office: 1,097 Days
• Field of Search: 438/48, 438/50, 438/53, 438/411, 438/689, 438/696, 438/700-701, 438/706-707, 438/710, 438/712-713, 438/694, 257/414-417, 216/2, 216/11, 216/17, 216/58, 216/79
• US Class Current: 438/50
• CPC Class Codes: B81C 1/00246 Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate
• CPC Class Codes: B81C 2201/014 by depositing an etch stop layer, e.g. silicon nitride, silicon oxide, metal
• CPC Class Codes: B81C 2203/0742 Interleave, i.e. simultaneously forming the micromechanical structure and the CMOS circuit
• CPC Class Codes: B81C 2203/075 the electronic processing unit being integrated into an element of the micromechanical structure
• CPC Class Codes: G01P 15/0802 Details
• CPC Class Codes: G01P 15/125 by capacitive pick-up
• CPC Class Codes: G01P 2015/084 the mass being suspended at more than one of its sides, e.g. membrane-type suspension, so as to permit multi-axis movement of the mass
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching

Abstract

A method for fabricating a micromachined structure. The method includes forming a circuitry layer having an upper etch-resistant layer on an upper surface of a substrate, directionally etching a portion of the circuitry layer exposed by the upper etch-resistant layer, and directionally etching a portion the substrate exposed by the upper etch-resistant layer with a deep reactive ion etch.

Claims

1. A method for fabricating a micromachined structure, comprising:

forming a circuitry layer having an upper etch-resistant layer on an upper surface of a substrate;

directionally etching a portion of the circuitry layer exposed by the upper etch-resistant layer to define first and second circuit microstructures;

directionally etching a portion the substrate exposed by the upper etch-resistant layer with a deep reactive ion etch; and

isotropically etching the substrate for a controlled period of time to completely remove substrate material from under the first circuit microstructure such that the substrate material under the second circuit microstructure is electrically isolated from any other substrate material.

2. The method of claim 1, wherein forming the circuitry layer includes forming the circuitry layer on a bulk silicon mass substrate.

3. The method of claim 1, wherein directionally etching the circuitry layer includes directionally etching the portion of the circuitry layer using a reactive ion etch.

4. The method of claim 1, wherein directionally etching the circuitry layer includes directionally etching the portion of the circuitry layer using a deep reactive ion etch.

5. The method of claim 1, wherein:

forming the circuitry layer includes forming a CMOS circuitry layer having an upper metallization layer;

directionally etching the portion of the circuitry layer includes directionally etching a portion of the CMOS circuitry layer exposed by the upper metallization layer; and

directionally etching the portion of the substrate includes directionally etching the portion of the substrate exposed by the upper metallization layer.

6. The method of claim 1, wherein directionally etching the portion of the substrate includes directionally etching the portion of the substrate exposed by the upper etch-resistant layer from the upper surface of the substrate to a lower surface of the substrate.

7. The method of claim 1, wherein directionally etching the portion of the substrate includes directionally etching the portion of the substrate exposed by the upper etch-resistant layer from the upper surface of the substrate to a point in the substrate.

8. The method of claim 7, further comprising back etching the substrate from a lower surface of the substrate to the point.

9. The method of claim 7, wherein etching the portion of the substrate exposed by the upper etch-resistant layer from the upper surface of the substrate to a point in the substrate includes etching the portion of the substrate from the upper surface to an insulating layer in the substrate.

10. The method of claim 9, further comprising etching a portion of the insulating layer.

11. A method for fabricating a micromachined structure, comprising:

forming a circuitry layer having an upper etch-resistant layer on an upper surface of a substrate;

directionally etching a portion of the circuitry layer exposed by the upper etch-resistant layer;

directionally etching a portion of the substrate exposed by the upper etch-resistant layer from the upper surface of the substrate to a point in the substrate; and

back etching the substrate from a lower surface of the substrate to the point.

12. A method for fabricating a micromachined structure, comprising:

forming a circuitry layer having an upper etch-resistant layer on an upper surface of a substrate;

directionally etching a portion of the circuitry layer exposed by the upper etch-resistant layer; and

directionally etching a portion of the substrate exposed by the upper etch-resistant layer from the upper surface of the substrate to an insulating layer in the substrate.

13. The method of claim 12, further comprising etching a portion of the insulating layer.

14. A method for fabricating a micromachined structure, comprising:

forming a CMOS circuitry layer on an upper surface of a substrate, the CMOS circuitry layer having a dielectric layer and an upper metallization layer; and

directionally etching a portion of the dielectric layer from an upper surface of the CMOS circuitry layer to a polysilicon region layer of the CMOS circuitry layer with a deep reactive ion etch.

15. The method of claim 14, further comprising etching the polysilicon region layer.

16. A method of fabricating a microelectromechanical device, comprising:

forming a micromachined structure layer on an upper surface of a substrate, wherein the micromachined structure layer includes an upper etch-resistant layer; and

etching a portion of the substrate exposed by the upper etch-resistant layer with a tapered etch.

17. A method for fabricating a micromachined structure, comprising:

forming a circuitry layer having an upper etch-resistant layer on an upper surface of a substrate;

directionally etching a protion of the circuitry layer exposed by the upper etch-resistant layer to define first and second circuit microstructures;

directionally etching a portion the substance exposed by the upper etch-resistant layer from the upper surface of the of the substrate to a lower surface of the substrate with a deep reactive ion etch; and

isotropically etchig the substrate for a controlled period of time to completely remove substrate material from under the first circuit microstructure.