Inverse integrated circuit fabrication process

• US 6,458,686 B1
• Filed: 04/30/2001
• Issued: 10/01/2002
• Est. Priority Date: 04/30/2001
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Piao, Fan
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Huynh, Andy
• Application Number:
  US09/845,980
• Time in Patent Office: 519 Days
• Field of Search: 438/622, 438/118, 438/151, 438/152, 438/384, 257/758
• US Class Current: 438/622
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 29/66575 where the source and drain or source and drain extensions are self-aligned to the sides of the gate H01L29/66606 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An inverse IC process provides surface uniformity. A method of fabricating an integrated circuit structure includes a number of interconnect layers and a number of transistors. The method includes providing interconnect layers above a substrate, providing a semiconductor layer above the interconnect layers and providing gate conductors on a top surface of the semiconductor layer. The top surface is opposite a bottom surface. The bottom surface is closer to the interconnect layers than the top surface.

Claims

1. A method of fabricating an integrated circuit structure including a plurality of interconnect layers, and a plurality of transistors, the method comprising steps in the following order:

providing a first interconnect layer above a substrate;

providing a first insulative layer above the first interconnect layer;

providing a second interconnect layer above the first interconnect layer;

providing a second insulative layer over the second interconnect layer;

providing a semiconductor film above the second insulative layer; and

providing the transistors at least partially in the semiconductor film, whereby surface topology uniformity is improved.

2. The method of claim 1, further comprising:

forming a conductive path from a top surface of the semiconductor film to a bottom surface of the semiconductive film before or after the providing the transistors step.

3. The method of claim 2, wherein the conductive path is coupled to the second interconnect layer.

4. The method of claim 1 further comprising:

providing a third interconnect layer above the first insulative layer; and

providing a third insulative layer above the third interconnect layer.

5. The method of claim 4 further comprising:

providing a fourth interconnect layer above the third insulative layer; and

providing a fourth insulative layer above the fourth interconnect layer.

6. The method of claim 5 further comprising:

providing a fifth interconnect layer above the semiconductor layer; and

providing a fifth insulative layer above the fifth interconnect layer.

7. The method of claim 2, wherein the conductive path includes a metal via.

8. The method of claim 7, wherein the via extends from a gate conductor to the second interconnect layer.

9. An inverse integrated circuit process of fabricating a large scale integrated circuit structure including a plurality of interconnect layers beneath a semiconductor layer and a plurality of gate conductors at least partially above the semiconductor layer, the process comprising:

providing the interconnect layers above a substrate;

providing the semiconductor layer above the interconnect layers; and

providing the gate conductors on a top surface of the semiconductor layer, the top surface being opposite a bottom surface, the bottom surface being closer to the interconnect layers than the top surface.

10. The process of claim 9 further comprising:

providing an insulative layer over the gate conductors.

11. The process of claim 10 further comprising:

providing an interconnect layer above the insulative layer.

12. The process of claim 9 further comprising:

providing a conductive path from the top surface to the bottom surface.

13. A method of manufacturing multilayer ultra-large scale integrated circuit structure comprising a substrate, a plurality of interconnect layers disposed above the substrate, a plurality of insulative layers, at least one of the insulative layers being between the interconnect layers, wherein interconnect vias are disposed through the insulating layers to be electrically coupled to at least one of the interconnect layers, and a semiconductor film having a top surface and a bottom surface, the top surface including a plurality of gate structures, the bottom surface being closer to the interconnect layers than the top surface, wherein a film conductive path extends from the top surface to the bottom surface, the film conductive path being electrically coupled to at least one of the interconnect vias, the method of manufacturing comprising the steps of:

providing a first interconnect layer of the interconnect layers above the substrate;

providing a first insulative layer of the insulating layers above the first interconnect layer;

providing a second interconnect layer of the interconnect layers above the first interconnect layer;

providing a second insulative layer of the insulating layers over the second interconnect layer;

providing the semiconductor film above the second insulative layer; and

providing the transistors at least partially disposed in the semiconductor film, the transistors including the gate structures whereby surface topology uniformity is improved.

14. The method of claim 13, wherein the conductive path is a doped region.

15. The integrated circuit of claim 14, wherein the conductive path is a P+ or N+ region.

16. The integrated circuit of claim 13, wherein the conductive path is a conductive substrate via.

17. The integrated circuit of claim 16, wherein the conductive substrate via includes a metal.

18. The integrated circuit of claim 17, wherein the metal includes tungsten, copper, or aluminum.

19. The integrated circuit of claim 13, further comprising:

a top interconnect layer above the top surface of the film.

20. The integrated circuit of claim 19, wherein the top interconnect layer is coupled to the gate structures.