Methods for making semiconductor chip having both self aligned silicide regions and non-self aligned silicide regions

• US 6,458,702 B1
• Filed: 03/09/2000
• Issued: 10/01/2002
• Est. Priority Date: 03/09/2000
• Status: Expired due to Term

• Current Assignee: Longitude Licensing Limited (Vector Capital Corporation)
• Original Assignee: Tower Semiconductor Limited
• Inventors: Aloni, Efraim
• Primary Examiner(s): Nguyen, Tuan H.
• Assistant Examiner(s): NGUYEN, THANH T
• Application Number:
  US09/522,245
• Time in Patent Office: 936 Days
• Field of Search: 438/682-683, 438/663-664, 438/655, 438/649, 438/651, 438/592, 438/595, 438/299-307, 438/230
• US Class Current: 438/682
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823443 silicided or salicided gate conductors
• CPC Class Codes: H01L 21/823468 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518

Abstract

A semiconductor process is provided that creates fully-salicided transistors. in a first region and partially-salicided transistors in a second region. Each of the fully-salicided transistors includes a salicided gate electrode and salicided active regions. Each of the partially-salicided transistors includes a salicided gate electrode and active regions that are free from salicide. A silicide blocking layer prevents the formation of salicide in the active regions of the partially-salicided transistors. The silicide blocking layer is deposited over the first and second regions, and then removed over the first region. The remaining portion of the silicide blocking layer over the second region is then etched back until the upper surfaces of the gate electrodes in the second region are exposed. The remaining portions of the silicide blocking layer covers the active regions in the second region. A refractory metal is then deposited over the resulting structure and reacted. As a result, salicide is formed on the active regions and gate electrodes in the first region, but only on the gate electrodes in the second region.

Claims

1. A method for forming a semiconductor device having a first region and a second region, the method comprising the steps of:

forming a plurality of conductive gates in the first region and the second region;

forming a first plurality of active regions in the first region;

forming a second plurality of active regions in the second region;

forming silicide blocking portions over the second plurality of active regions by

depositing a silicide blocking layer over the first dielectric layer, wherein the silicide blocking layer extends over the first region and the second region;

etching a portion of the silicide blocking layer in the first region;

depositing a spacer oxide layer over the semiconductor device;

etching the spacer oxide layer and the silicide blocking layer to expose the plurality of conductive gates, and the plurality of active regions in the first region; and

forming a plurality of salicide layers overlying the plurality of polysilicon gates and the first plurality of active regions.

2. The method of claim 1, further comprising the steps of depositing a first dielectric layer over an upper surface of the semiconductor device, wherein the first dielectric layer overlies the plurality of conductive gates and wherein the first dielectric layer extends over the first region and the second region.

3. The method of claim 2, further comprising the step of depositing a second dielectric layer over the first dielectric layer.

4. The method of claim 3, wherein the first dielectric layer is an oxide layer and the second dielectric layer is a nitride layer.

5. The method of claim 1, wherein the step of forming a plurality of silicide layers overlying the plurality of polysilicon gates and the first plurality of active regions, further comprises the steps of:

depositing a metal layer over the semiconductor device;

annealing the metal layer to form the plurality of silicide layers.

6. The method of claim 5, wherein metal layer is a titanium layer.

7. The method of claim 1, wherein the silicide blocking layer has a first thickness over the conductive gates and a second thickness over the active regions.

8. The method of claim 7, wherein the first thickness is less than the second thickness.

9. The method of claim 8, wherein the first thickness is approximately {fraction (1/10)} of the second thickness.

10. The method of claim 1, wherein the silicide blocking layer is substantially planar.