Methods of forming ultra-thin buffer oxide layers for gate dielectrics

• US 6,458,717 B1
• Filed: 07/13/2000
• Issued: 10/01/2002
• Est. Priority Date: 07/13/2000
• Status: Expired due to Term

• Current Assignee: Chartered Semiconductor Manufacturing Incorporated (Mamoura Diversified Global Holding PJSC)
• Original Assignee: Chartered Semiconductor Manufacturing Incorporated (Mamoura Diversified Global Holding PJSC)
• Inventors: Li, Xia, Lee, James Yong Meng, Zhang, Yunqzang
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): LEE, GRANVILL D
• Application Number:
  US09/615,810
• Time in Patent Office: 810 Days
• Field of Search: 438/778, 438/585, 438/426, 438/450, 438/787, 438/473, 438/522
• US Class Current: 438/778
• CPC Class Codes: H01L 21/022 the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides adhesion layers or buffer layers H01L21/02304, H01L21/02362
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/28176 with a treatment, e.g. annealing, after the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/28202 in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
• CPC Class Codes: H01L 21/28238 with sacrificial oxide
• CPC Class Codes: H01L 21/3144 on silicon
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material

Abstract

A first option is a method of forming an ultra thin buffer oxide layer comprises the following steps. A silicon substrate having STI regions formed therein separating at least one active area is provided. The silicon substrate has an upper surface. A sacrificial oxide layer is formed over the silicon substrate and the STI regions. Oxygen is implanted within the silicon substrate. The oxygen implant having a peak concentration proximate the upper surface of the silicon substrate. The sacrificial oxide layer is stripped and removed. A gate dielectric layer is formed over the silicon substrate. A conductor layer is deposited over the gate dielectric layer. The structure is annealed to form ultra-thin buffer oxide layer between the silicon substrate and the gate dielectric layer. A second option is a method of forming an ultra-thin buffer oxide layer, comprises the following steps. A silicon substrate having STI regions formed therein separating at least one active area is provided. The silicon substrate has an upper surface. A gate dielectric layer is formed over the silicon substrate and the STI regions. A sacrificial oxide layer is formed over the gate dielectric layer. Oxygen is implanted within the silicon substrate. The oxygen implant having a peak concentration proximate the upper surface of the silicon substrate. The sacrificial oxide layer is stripped and removed. A conductor layer is deposited over the gate dielectric layer. The structure is annealed to form ultra-thin buffer oxide layer between the silicon substrate and the gate dielectric layer.

Claims

1. A method of forming an ultra-thin buffer oxide layer, comprising the following steps:

providing a silicon substrate having STI regions formed therein separating at least one active area;

said silicon substrate having an upper surface;

forming a sacrificial oxide layer over said silicon substrate and said STI regions;

implanting oxygen within said silicon substrate;

said oxygen implant having a peak concentration proximate said upper surface of said silicon substrate;

stripping and removing said sacrificial oxide layer;

forming a gate dielectric layer over said silicon substrate;

depositing a conductor layer over said gate dielectric layer;

annealing the structure to form ultra-thin buffer oxide layer between said silicon substrate and said gate dielectric layer.

2. The method of claim 1, wherein said sacrificial oxide layer is from about 95 to 105 Å

thick;

said gate dielectric layer is from about 10 to 50 Å

;

said conductor layer is from about 2400 to 2600 Å

thick; and

said ultra-thin buffer oxide layer is from about 3 to 15 Å

thick.

3. The method of claim 1, wherein said sacrificial oxide layer is about 100 Å

thick;

said gate dielectric layer is from about 20 to 30 Å

;

said conductor layer is about 2500 Å

thick; and

said ultra-thin buffer oxide layer is from about 3 to 10 Å

thick.

4. The method of claim 1, wherein said oxygen implantation is performed at a dose from about 1E¹⁴ to 1E¹⁶ cm⁻

2 and an energy from about 10 to 50 keV.

5. The method of claim 1, wherein said gate dielectric layer is formed using a Rapid Thermal Nitridation (RTN) process.

6. The method of claim 1, wherein said annealing step is performed from about 800 to 900°

C. for about 10 to 20 seconds.

7. The method of claim 1, wherein the gate dielectric layer is comprised of SiN.

8. A method of forming an ultra-thin buffer oxide layer, comprising the following steps:

providing a silicon substrate having STI regions formed therein separating at least one active area;

said silicon substrate having an upper surface;

forming a sacrificial oxide layer over said silicon substrate and said STI regions;

said sacrificial oxide layer having a thickness of from about 95 to 105 Å

;

implanting oxygen within said silicon substrate;

said oxygen implant having a peak concentration proximate said upper surface of said silicon substrate;

stripping and removing said sacrificial oxide layer;

forming a gate dielectric layer over said silicon substrate;

said gate dielectric layer having a thickness of from about 10 to 50 Å

;

depositing a conductor layer over said gate dielectric layer;

said conductor layer having a thickness of from about 2400 to 2600 Å

;

annealing the structure to form ultra-thin buffer oxide layer between said silicon substrate and said gate dielectric layer;

said ultra-thin buffer oxide layer having a thickness of from about 3 to 15 Å

thick.

9. The method of claim 8, wherein said sacrificial oxide layer is about 100 Å

thick;

said gate dielectric layer is from about 20 to 30 Å

;

said conductor layer is about 2500 Å

thick; and

said ultra-thin buffer oxide layer is from about 3 to 10 Å

thick.

10. The method of claim 8, wherein said oxygen implantation is performed at a dose from about 1E¹⁴ to 1E¹⁶ cm⁻

2 and an energy from about 10 to 50 keV.

11. The method of claim 8, wherein said gate dielectric layer is formed using a Rapid Thermal Nitridation (RTN) process.

12. The method of claim 8, wherein said annealing step is performed from about 800 to 900°

C. for about 10 to 20 seconds.

13. The method of claim 8, wherein the gate dielectric layer is comprised of SiN.

18. The method of claim 12, wherein said gate dielectric layer formation includes the steps of:

performing a Rapid Thermal Nitridation (RTN) of said silicon substrate; and

forming a gate dielectric layer over said silicon substrate by chemical vapor deposition.

14. A method of forming an ultra-thin buffer oxide layer, comprising the following steps:

providing a silicon substrate having STI regions formed therein separating at least one active area;

said silicon substrate having an upper surface;

forming a gate dielectric layer over said silicon substrate and said STI regions;

forming a sacrificial oxide layer over said gate dielectric layer;

implanting oxygen within said silicon substrate;

said oxygen implant having a peak concentration proximate said upper surface of said silicon substrate;

stripping and removing said sacrificial oxide layer;

depositing a conductor layer over said gate dielectric layer;

annealing the structure to form ultra-thin buffer oxide layer between said silicon substrate and said gate dielectric layer.

15. The method of claim 14, wherein said gate dielectric layer is from about 10 to 50 Å

;

said sacrificial oxide layer is from about 95 to 105 Å

thick;

said conductor layer is from about 2400 to 2600 Å

thick; and

said ultra-thin buffer oxide layer is from about 3 to 15 Å

thick.

16. The method of claim 14, wherein said gate dielectric layer is from about 20 to 30 Å

;

said sacrificial oxide layer is about 100 Å

thick;

said conductor layer is about 2500 Å

thick; and

said ultra-thin buffer oxide layer is from about 3 to 10 Å

thick.

17. The method of claim 14, wherein said oxygen implantation is performed at a dose from about 1E^-to 1E¹⁶ cm⁻

2 and an energy from about 10 to 50 keV.

19. The method of claim 14, wherein the gate dielectric layer is comprised of SiN.

20. A method of forming an ultra-thin buffer oxide layer, comprising the following steps:

providing a silicon substrate having STI regions formed therein separating at least one active area;

said silicon substrate having an upper surface;

forming a gate dielectric layer over said silicon substrate and said STI regions;

said gate dielectric layer having a thickness of from about 10 to 50 Å

;

forming a sacrificial oxide layer over said gate dielectric layer;

said sacrificial oxide layer having a thickness of from about 95 to 105 Å

;

implanting oxygen within said silicon substrate;

said oxygen implant having a peak concentration proximate said upper surface of said silicon substrate;

stripping and removing said sacrificial oxide layer;

depositing a conductor layer over said gate dielectric layer;

said conductor layer having a thickness of from about 2400 to 2600 Å

;

annealing the structure to form ultra-thin buffer oxide layer between said silicon substrate and said gate dielectric layer;

said ultra-thin buffer oxide layer having a thickness from about 3 to 15 Å

.

21. The method of claim 20, wherein said gate dielectric layer is from about 20 to 30 Å

;

said sacrificial oxide layer is about 100 Å

thick;

said conductor layer is about 2500 Å

thick; and

said ultra-thin buffer oxide layer is from about 3 to 10 Å

thick.

22. The method of claim 20, wherein said oxygen implantation is performed at a dose from about 1E¹⁴ to 1E¹⁶ cm⁻

2 and an energy from about 10 to 50 keV.

23. The method of claim 20, wherein said gate dielectric layer formation includes the steps of:

performing a Rapid Thermal Nitridation (RTN) of said silicon substrate; and

forming a gate dielectric layer over said silicon substrate by chemical vapor deposition.

24. The method of claim 20, wherein the gate dielectric layer is comprised of SiN.

25. A method of forming an ultra-thin buffer oxide layer, comprising the following steps:

providing a silicon substrate having an upper surface;

forming a sacrificial oxide layer over said silicon substrate;

implanting oxygen within said silicon substrate;

said oxygen implant having a peak concentration proximate said upper surface of said silicon substrate;

stripping and removing said sacrificial oxide layer;

forming a gate dielectric layer over said silicon substrate;

depositing a conductor layer over said gate dielectric layer;

annealing the structure whereby said oxygen implant facilitates formation of an ultra-thin buffer oxide layer between said silicon substrate and said gate dielectric layer.

26. The method of claim 25, wherein said sacrificial oxide layer is from about 95 to 105 Å

thick;

said gate dielectric layer is from about 10 to 50 Å

;

said conductor layer is from about 2400 to 2600 Å

thick; and

said ultra-thin buffer oxide layer is from about 3 to 15 Å

thick.

27. The method of claim 25, wherein said sacrificial oxide layer is about 100 Å

thick;

said gate dielectric layer is from about 20 to 30 Å

;

said conductor layer is about 2500 Å

thick; and

said ultra-thin buffer oxide layer is from about 3 to 10 Å

thick.

28. The method of claim 25, wherein said oxygen implantation is performed at a dose from about 1E¹⁴ to 1E¹⁶ cm⁻

2 and an energy from about 10 to 50 keV.

29. The method of claim 25, wherein said gate dielectric layer is formed using a Rapid Thermal Nitridation (RTN) process.

30. The method of claim 25, wherein said annealing step is performed from about 800 to 900°

C. for about 10 to 20 seconds.