High density signal routing

• US 6,459,049 B1
• Filed: 06/20/2001
• Issued: 10/01/2002
• Est. Priority Date: 06/20/2001
• Status: Active Grant

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Miller, Leah M., Thurairajaratnam, Aritharan, Ghahghahi, Farshad, Fulcher, Edwin M.
• Primary Examiner(s): PALADINI, ALBERT WILLIAM
• Application Number:
  US09/885,299
• Time in Patent Office: 468 Days
• Field of Search: 257/691, 361/794, 361/777, 428/901, 174/261, 174/262, 174/263
• US Class Current: 174/261
• CPC Class Codes: H01R 31/06 Intermediate parts for linking two coupling parts, e.g. adapter with a holder adapted for supporting apparatus to which its counterpart is attached H01R33/94
• CPC Class Codes: H05K 1/0216 Reduction of cross-talk, noise or electromagnetic interference grounding H05K1/0215
• CPC Class Codes: H05K 1/112 directly combined with via connections
• CPC Class Codes: H05K 1/117 Pads along the edge of rigid circuit boards, e.g. for pluggable connectors
• CPC Class Codes: H05K 2201/09236 Parallel layout layout of balanced signal pairs H05K1/0245; superposed layout H05K2201/09672
• CPC Class Codes: H05K 2201/09281 Layout details of a single conductor meander H05K2201/09263; layout details of angles or corners H05K2201/09272
• CPC Class Codes: H05K 2201/09727 Varying width along a single conductor; Conductors or pads having different widths

Abstract

A structure for receiving electrical signals near a central portion of the structure and distributing the electrical signals to a peripheral portion of the structure. The structure has a first set of contacts arranged in an array near the central portion of the structure. Electrically conductive traces connect the first set of contacts to a second set of contacts, where each of the electrically conductive traces has at least a first segment, a second segment, and a third segment. The first segment of each of the electrically conductive traces has relatively narrow width and spacing. The first segment of each of the electrically conductive traces is connected on a first end of the first segment to one of the first set of contacts and on a second end of the first segment to the second segment of each of the electrically conductive traces. The second segment of each of the electrically conductive traces has relatively intermediate width and spacing. The second segment of each of the electrically conductive traces is connected on a first end of the second segment to the second end of the first segment and on a second end of the second segment to the third segment of each of the electrically conductive traces. The third segment of each of the electrically conductive traces has relatively wide width and spacing. The third segment of each of the electrically conductive traces is connected on a first end of the third segment to the second end of the second segment and on a second end of the third segment to one of the second set of contacts.

Claims

1. A circuit board for receiving electrical data signals near a central portion of the circuit board that receives a packaged integrated circuit, and the electrical signals are transferred between a peripheral portion of the circuit board and the packaged integrated circuit:

a first set of contacts arranged in an array in the central portion of the circuit board,

a second set of contacts in the peripheral portion of the circuit board, and

electrically conductive traces connecting the first set of contacts to the second set of contacts, wherein each of the electrically conductive traces has at least a first segment, a second segment, and a third segment,

the first segment of each of the electrically conductive traces having a relatively narrow width and spacing and connected to one of the first set of contacts on a first end of the first segment and to the second segment of each of the electrically conductive traces on a second end of the first segment,

the second segment of each of the electrically conductive traces having a relatively intermediate width and spacing and connected to the second end of the first segment of each of the electrically conductive traces on a first end of the second segment and to the third segment of each of the electrically conductive traces on a second end of the second segment, and

the third segment of each of the electrically conductive traces having a relatively wide width and spacing and connected to the second end of the second segment of each of the electrically conductive traces on a first end of the third segment and to one of the second set of contacts on a second end of the third segment.

2. The circuit board of claim 1, wherein the electrically conductive traces have more than three segments, where the segments generally gradually increase in width and spacing from the central portion of the circuit board to the peripheral portion of the circuit board.

3. The circuit board of claim 1, wherein the relatively narrow width is within a low end of manufacturing limits for the circuit board.

4. The circuit board of claim 1, wherein the relatively narrow spacing is within a low end of manufacturing limits for the circuit board.

5. The circuit board of claim 1, wherein the relatively intermediate width is within a mid-range of manufacturing limits for the circuit board.

6. The circuit board of claim 1, wherein the relatively intermediate spacing is within a mid-range of manufacturing limits for the circuit board.

7. The circuit board of claim 1, wherein the relatively wide width is within a high end of manufacturing limits for the circuit board.

8. The circuit board of claim 1, wherein the relatively wide spacing is within a high end of manufacturing limits for the circuit board.

9. An integrated circuit package for receiving electrical data signals near a central portion of the integrated circuit package that receives an integrated circuit, and the electrical signals are transferred between a peripheral portion of the integrated circuit package and the integrated circuit:

a first set of contacts arranged in an array in the central portion of the integrated circuit package,

a second set of contacts in the peripheral portion of the integrated circuit package, and

electrically conductive traces connecting the first set of contacts to the second set of contacts, wherein each of the electrically conductive traces has at least a first segment, a second segment, and a third segment,

the first segment of each of the electrically conductive traces having a relatively narrow width and spacing and connected to one of the first set of contacts on a first end of the first segment and to the second segment of each of the electrically conductive traces on a second end of the first segment,

the second segment of each of the electrically conductive traces having a relatively intermediate width and spacing and connected to the second end of the first segment of each of the electrically conductive traces on a first end of the second segment and to the third segment of each of the electrically conductive traces on a second end of the second segment, and

the third segment of each of the electrically conductive traces having a relatively wide width and spacing and connected to the second end of the second segment of each of the electrically conductive traces on a first end of the third segment and to one of the second set of contacts on a second end of the third segment.

10. The integrated circuit package of claim 9, wherein the electrically conductive traces have more than three segments, where the segments generally gradually increase in width and spacing from the central portion of the integrated circuit package to the peripheral portion of the integrated circuit package.

11. The integrated circuit package of claim 9, wherein the relatively narrow width is within a low end of manufacturing limits for the integrated circuit package.

12. The integrated circuit package of claim 9, wherein the relatively narrow spacing is within a low end of manufacturing limits for the integrated circuit package.

13. The integrated circuit package of claim 9, wherein the relatively intermediate width is within a mid-range of manufacturing limits for the integrated circuit package.

14. The integrated circuit package of claim 9, wherein the relatively intermediate spacing is within a mid-range of manufacturing limits for the integrated circuit package.

15. The integrated circuit package of claim 9, wherein the relatively wide width is within a high end of manufacturing limits for the integrated circuit package.

16. The integrated circuit package of claim 9, wherein the relatively wide spacing is within a high end of manufacturing limits for the integrated circuit package.