Negative-differential-resistance heterojunction bipolar transistor with topee-shaped current-voltage characteristics

• US 6,459,103 B1
• Filed: 01/26/2000
• Issued: 10/01/2002
• Est. Priority Date: 01/10/2000
• Status: Expired due to Term

• Current Assignee: National Science Council
• Original Assignee: National Science Council
• Inventors: Wang, Wei-Chou, Cheng, Shiou-Ying, Liu, Wen-Chau
• Primary Examiner(s): Lee, Eddie
• Assistant Examiner(s): Baumeister, Bradley W.
• Application Number:
  US09/491,441
• Time in Patent Office: 979 Days
• Field of Search: 257/582, 257/583, 257/198, 257/197, 257/591-593, 257/14, 257/25, 257/12
• US Class Current: 257/197
• CPC Class Codes: H01L 29/7371 Vertical transistors

Abstract

An InP/InGaAlAs heterojunction bipolar transistor with the characteristics of amplification and negative-differential-resistance phenomenon is presented in the invention. The 3-terminal current-voltage characteristics of the heterojunction bipolar transistor can be controlled by the applied base current. In the large collector current regime, the heterojunction bipolar transistor has the characteristics as similar to conventional bipolar junction transistors. However, in a small collector current regime, both the transistor active region and negative-differential-resistance loci are observed. The negative-differential-resistance phenomenon is caused by the insertion of a thin base layer and a δ-doped sheet. Moreover, the use of a setback layer with a thickness of 50 Å added at the emitter-base junction can suppress the diffusion of doping impurity in the base and reduce the potential spike at emitter-base heterojunction so as to improve the confinement of holes injected from base to emitter.

Claims

1. A heterojunction bipolar transistor with topee-shaped negative-differential-resistance characteristics comprising:

a substrate;

a sub-collector layer located on the surface of the substrate;

a collector control layer located on the surface of the sub-collector layer;

a base control layer located on the surface of the collector control layer and with a setback layer;

an emitter control layer located on the surface of the base control layer and with a δ

-doped sheet; and

an ohmic contract layer located on the surface of the emitter control layer.

2. The heterojunction bipolar transistor as defined in claim 1, wherein the substrate is an n⁺-type InP substrate.

3. The heterojunction bipolar transistor as defined in claim 1, wherein the substrate is an n⁺-type GaAs substrate.

4. The heterojunction bipolar transistor as defined in claim 1, wherein the sub-collector layer is an n⁺-type InP sub-collector layer.

5. The heterojunction bipolar transistor as defined in claim 1, wherein the sub-collector layer is an n⁺-type InGaAs sub-collector layer.

6. The heterojunction bipolar transistor as defined in claim 1, wherein the sub-collector layer is an n⁺-type GaAs sub-collector layer.

7. The heterojunction bipolar transistor as defined in claim 1, wherein the collector control layer is an n⁺-type In_0.53Ga_0.23Al_0.24As collector control layer.

8. The heterojunction bipolar transistor as defined in claim 1, wherein the collector layer is an n-type InGaAs collector control layer.

9. The heterojunction bipolar transistor as defined in claim 1, wherein the collector control layer is an n-type InP collector control layer.

10. The heterojunction bipolar transistor as defined in claim 1, wherein the collector control layer is an n-type GaAs collector control layer.

11. The heterojunction bipolar transistor as defined in claim 1, wherein the collector control layer is an n-type InGaP collector control layer.

12. The heterojunction bipolar transistor as defined in claim 1, wherein the collector control layer is an n-type AlGaAs collector control layer.

13. The heterojunction bipolar transistor as defined in claim 1, wherein the base control layer is a p⁺-type In_0.53Ga_0.23Al_0.24As base control layer.

14. The heterojunction bipolar transistor as defined in claim 1, wherein the base control layer is a p⁺-type InGaAs base control layer.

15. The heterojunction bipolar transistor as defined in claim 1, wherein the base control layer is a p⁺-type GaAs base control layer.

16. The heterojunction bipolar transistor as defined in claim 1, wherein the base control layer is a p⁺-type InGaP base control layer.

17. The heterojunction bipolar transistor as defined in claim 1, wherein the base control layer is a p⁺-type AlGaAs base control layer.

18. The heterojunction bipolar transistor as defined in claim 1, wherein the base control layer comprises:

a first setback layer;

a p⁺-type In_0.53Ga_0.23Al_0.24As layer located on the first setback layer; and

a second setback layer located on the p⁺-type In_0.53Ga_0.23Al_0.24As layer, wherein the p⁺-type In_0.53Ga_0.23Al_0.24As layer is located between the first setback layer and the second setback layer.

19. The heterojunction bipolar transistor as defined in claim 18, wherein the first setback layer and the second setback layer are undoped In_0.53Ga_0.23Al_0.24As layers.

20. The heterojunction bipolar transistor as defined in claim 1, wherein the base control layer comprises:

a first setback layer;

a p⁺-type InGaAs layer located on the first setback layer; and

a second setback layer located on the p⁺-type InGaAs layer, wherein the p⁺-type InGaAs layer is located between the first setback layer and the second setback layer.

21. The heterojunction bipolar transistor as defined in claim 20, wherein the first setback layer and the second setback layer are undoped In_0.53Ga_0.23Al_0.24As layers.

22. The heterojunction bipolar transistor as defined in claim 1, wherein the base control layer comprises:

a first setback layer;

a p⁺-type GaAs layer located on the first setback layer;

a second setback layer located on the p⁺-type GaAs layer, wherein the p⁺-type GaAs layer is located between the first setback layer and the second setback layer.

23. The heterojunction bipolar transistor as defined in claim 22, wherein the first setback layer and the second setback layer are undoped GaAs layers.

24. The heterojunction bipolar transistor as defined in claim 22, wherein the first setback layer and the second setback layer are undoped InGaP layers.

25. The heterojunction bipolar transistor as defined in claim 1, wherein the base control layer comprises:

a first setback layer;

a p⁺-type AlGaAs layer located on the first setback layer; and

a second setback layer located on the p⁺-type AlGaAs layer, wherein the p⁺-type AlGaAs layer is located between the first setback layer and the second setback layer.

26. The heterojunction bipolar transistor as defined in claim 25, wherein the first setback layer and the second setback layer are undoped GaAs layers.

27. The heterojunction bipolar transistor as defined in claim 25, wherein the first setback layer and the second setback layer are undoped InGaP layers.

28. The heterojunction bipolar transistor as defined in claim 1, wherein the thickness of the base control layer is 100˜

400 Å

.

29. The heterojunction bipolar transistor as defined in claim 1, wherein the emitter control layer is an n-type InP emitter control layer.

30. The heterojunction bipolar transistor as defined in claim 1, wherein the emitter control layer is an n-type InAlAs emitter control layer.

31. The heterojunction bipolar transistor as defined in claim 1, wherein the emitter control layer is an n-type GaAs emitter control layer.

32. The heterojunction bipolar transistor as defined in claim 1, wherein the emitter control layer is an n-type AlGaAs layer.

33. The heterojunction bipolar transistor as defined in claim 1, wherein the emitter control layer is an n-type InGaP emitter control layer.

34. The heterojunction bipolar transistor as defined in claim 1, wherein the emitter control layer comprises:

a δ

-doped sheet; and

an n-type InP layer.

35. The heterojunction bipolar transistor as defined in claim 34, wherein the concentration of the δ

-doped sheet is 10¹¹ cm<sup>−

2</sup>˜

10¹³ cm<sup>−

2</sup>.

36. The heterojunction bipolar transistor as defined in claim 1, wherein the emitter control layer comprises:

a δ

-doped sheet; and

an n-type InGaAs layer.

37. The heterojunction bipolar transistor as defined in claim 36, wherein the concentration of the δ

-doped sheet layer is 10¹¹ cm<sup>−

2</sup>˜

10¹³ cm<sup>−

2</sup>.

38. The heterojunction bipolar transistor as defined in claim 1, wherein the emitter control layer comprises:

a δ

-doped sheet; and

an n-type InAlAs layer.

39. The heterojunction bipolar transistor as defined in claim 38, wherein the concentration of the δ

-doped sheet is 10¹¹ cm<sup>−

2</sup>˜

10¹³ cm<sup>−

2</sup>.

40. The heterojunction bipolar transistor as defined in claim 1, wherein the emitter control layer comprises:

a δ

-doped sheet; and

an n-type GaAs layer.

41. The heterojunction bipolar transistor as defined in claim 40, wherein the concentration of the δ

-doped sheet is 10¹¹ cm<sup>−

2</sup>˜

10¹³ cm<sup>−

2</sup>.

42. The heterojunction bipolar transistor as defined in claim 1, wherein the emitter control layer comprises:

a δ

-doped sheet; and

an n-type AlGaAs layer.

43. The heterojunction bipolar transistor as defined in claim 42, wherein the concentration of the δ

-doped sheet is 10¹¹ cm<sup>−

2</sup>˜

10¹³ cm<sup>−

2</sup>.

44. The heterojunction bipolar transistor as defined in claim 1, wherein the emitter control layer comprises:

a δ

-doped sheet; and

an n-type InGaP layer.

45. The heterojunction bipolar transistor as defined in claim 44, wherein the concentration of the δ

-doped sheet is 10¹¹ cm<sup>−

2</sup>˜

10¹³ cm<sup>m−

2</sup>.

46. The heterojunction bipolar transistor as defined in claim 1, wherein the ohmic contact layer is an n⁺-type InGaAs layer.

47. The heterojunction bipolar transistor as defined in claim 1, wherein the ohmic contact layer is an n⁺-type GaAs layer.