Semiconductor storage element

• US 6,459,110 B1
• Filed: 06/08/2000
• Issued: 10/01/2002
• Est. Priority Date: 07/30/1999
• Status: Expired due to Fees

• Current Assignee: LAPIS Semiconductor Co., Ltd. (ROHM Co., Ltd.)
• Original Assignee: OKI Electric Industry Company Limited
• Inventors: Tani, Kouichi
• Primary Examiner(s): Lee, Eddie
• Assistant Examiner(s): NGUYEN, JOSEPH H
• Application Number:
  US09/589,401
• Time in Patent Office: 845 Days
• Field of Search: 257/295, 365/65, 365/145, 365/182, 365/184
• US Class Current: 257/295
• CPC Class Codes: G11C 11/22 using ferroelectric elements
• CPC Class Codes: H10B 53/00 Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors

Abstract

A memory cell array, in which a voltage that can reverse polarization is applied only to a memory cell that is an object of data writing. A semiconductor storage element is formed by a ferroelectric capacitor, a selection transistor and a control transistor. The ferroelectric capacitor is structured to be provided with a ferroelectric layer between an upper electrode and a lower electrode. The selection transistor is provided with a first main electrode, a second main electrode and a control electrode. The control transistor is provided with a first main electrode, a second main electrode and a control electrode. The lower electrode of the ferroelectric capacitor is connected with the first main electrode of the selection transistor. The second main electrode of the selection transistor is connected with the control electrode of the control transistor.

Claims

1. A memory cell comprising:

a ferroelectric capacitor;

a selection transistor;

a control transistor;

a sense amplifier coupled to a first main electrode of the control transistor; and

a read line coupled to a second main electrode of the control transistor,

wherein one electrode of said ferroelectric capacitor is connected with a first main electrode of said selection transistor, the other electrode of said ferroelectric capacitor is connected with a plate line which is different from the read line, and a second main electrode of said selection transistor is connected with a control electrode of said control transistor.

7. A memory cell according to claim 1, wherein said plate line has a voltage which varies.

2. A memory cell comprising:

a ferroelectric capacitor;

a first transistor;

a second transistor;

a bit line coupled to a first main electrode of the second transistor; and

a read line coupled to a second main electrode of the second transistor,

wherein one electrode of two electrodes of said ferroelectric capacitor is connected with one main electrode of two main electrodes of said first transistor, the other electrode of said ferroelectric capacitor is connected with a plate line which is different from said read line and said bit line, and another main electrode of said first transistor is connected with a control electrode of said second transistor, said plate line having a voltage which varies.

3. A memory cell according to claim 2, wherein said first transistor is a field effect transistor, and the two main electrodes of said first transistor are a source electrode and a drain electrode.

4. A memory cell according to claim 2, wherein said second transistor is a field effect transistor, and the control electrode of said second transistor is a gate electrode.

8. A memory cell according to claim 3, wherein said second transistor has its backgate electrode coupled to ground.

5. A memory cell comprising:

a ferroelectric capacitor structured to have a ferroelectric layer between an upper electrode and a lower electrode;

a selection transistor having a first main electrode, a second main electrode and a control electrode;

a control transistor having a first main electrode, a second main electrode and a control electrode; and

first and second voltage lines coupled to the first and second main electrodes of said control transistor, respectively,

wherein the lower electrode of said ferroelectric capacitor is connected with the first main electrode of said selection transistor, the upper electrode of said ferroelectric capacitor is connected with a plate line which is different from said first and second voltage lines and the second main electrode of said selection transistor is connected with the control electrode of said control transistor.

9. A memory cell according to claim 5, wherein said plate line has a voltage which varies.

6. A memory cell array comprising a plurality of memory cells:

(a) each memory cell including;

a ferroelectric capacitor structured to have a ferroelectric layer between an upper electrode and a lower electrode;

a selection transistor having a first main electrode , a second main electrode and a control electrode; and

a control transistor having a first main electrode, a second main electrode, a control electrode and a back gate electrode;

wherein the lower electrode of said ferroelectric capacitor is connected with the first main electrode of said selection transistor , and the second main electrode of said selection transistor is connected with the control electrode of said control transistor;

(b) a power supply;

(c) a selection transistor driving section;

(d) a sense amplifier;

(e) a data readout driving section; and

(f) an earth terminal,

wherein the upper electrode of said ferroelectric capacitor of each memory cell is connected with said power supply by a respective plate line, the control electrode of said selection transistor of each memory cell is connected with said selection transistor driving section by a respective common word line shared by plural memory cells, the first main electrode of said control transistor of each memory cell is connected with said sense amplifier by a respective common bit line shared by plural memory cells, the second main electrode of said control transistor of each memory cell is connected with said data readout driving section by a respective common read line shared by plural memory cells, and the back gate electrode of said control transistor of each memory cell is connected with said earth terminal.

10. A memory cell according to claim 6, wherein said respective plate line for each memory cell has a voltage which varies.