Power MOSFET

• US 6,459,142 B1
• Filed: 07/14/2000
• Issued: 10/01/2002
• Est. Priority Date: 01/14/1998
• Status: Expired due to Term

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Tihanyi, Jenoe
• Primary Examiner(s): Lee, Eddie
• Assistant Examiner(s): Lee, Eugene
• Application Number:
  US09/616,620
• Time in Patent Office: 809 Days
• Field of Search: 257/621, 257/513, 257/514, 257/520, 257/774, 257/328, 257/302, 257/330
• US Class Current: 257/621
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/41 characterised by their shape, relative sizes or dispositions
• CPC Class Codes: H01L 29/4175 for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The power MOSFET has a semiconductor layer formed on a highly doped semiconductor substrate of a first conductivity type. The semiconductor layer is itself of the other conductivity type and a highly doped source zone of the other conductivity type and a highly doped drain zone of the other conductivity type are formed in the semiconductor layer. The power MOSFET also has a gate electrode. A metallically conductive connection runs between the source zone and the semiconductor substrate, so that the power MOSFET is in the form of a source-down MOSFET, and the heat can be dissipated via the semiconductor substrate or a cooling fin fitted there.

Claims

1. A power MOSFET, comprising:

a highly doped semiconductor substrate of a first conductivity type having a surface;

an electrode disposed on said surface of said semiconductor substrate;

a semiconductor layer of a second conductivity type on said semiconductor substrate;

a highly doped source zone of the second conductivity type and a highly doped drain zone of the second conductivity type formed in said semiconductor layer;

a semiconductor zone of the first conductivity type and a gate electrode above said semiconductor zone, said gate electrode having an edge spaced apart from said drain zone by a spacing distance; and

a highly metallic conductive connection between said source zone and said surface of said semiconductor substrate, said source zone being electrically connected to said electrode disposed on said surface of said semiconductor substrate, opposite said semiconductor layer.

2. The power MOSFET according to claim 1, which further comprises an insulator layer on said semiconductor layer, said gate electrode being formed in said insulator layer.

3. The power MOSFET according to claim 1, wherein said gate electrode is formed in a trench in said semiconductor layer.

4. The power MOSFET according to claim 1, wherein said conductive connection is a highly doped semiconductor zone of the first conductivity type.

5. The power MOSFET according to claim 1, wherein said conductive connection is a trench with out-diffused dopant of the first conductivity type and filled with silicon selected from the group consisting of polycrystalline and monocrystalline silicon.

6. The power MOSFET according to claim 1, wherein said conductive connection is a trench at least partially filled with a metal.

7. The power MOSFET according to claim 6, wherein said metal is tungsten.

8. The power MOSFET according to claim 6, wherein an interior of said trench is filled with one of an insulator and polycrystalline silicon doped with dopant of the first conductivity type.

9. The power MOSFET according to claim 1, wherein said conductive connection is a trench at least partially filled with a highly conductive layer.

10. The power MOSFET according to claim 9, wherein said highly conductive layer is formed of titanium nitride.

11. The power MOSFET according to claim 9, wherein an interior of said trench is filled with one of an insulator and polycrystalline silicon doped with dopant of the first conductivity type.

12. The power MOSFET according to claim 1, which comprises a cooling device connected to said semiconductor substrate.

13. The power MOSFET according to claim 12, wherein said cooling device is composed of metal.

14. The power MOSFET according to claim 3, wherein said semiconductor layer is more lightly doped between said drain zone and said gate than said drain zone.

15. The power MOSFET according to claim 4, which comprises a buried metal area between said source zone and said highly doped semiconductor zone.

16. The power MOSFET according to claim 5, which comprises a buried metal area between said source zone and said silicon filling said trench.

17. The power MOSFET according to claim 1, wherein said spacing distance between said drain zone and said edge of said gate electrode is 0.1 μ

m to 5 μ

m.

18. The power MOSFET according to claim 2, wherein a thickness of said insulator layer below said gate electrode increases continuously in a direction towards said drain zone.

19. The power MOSFET according to claim 2, wherein a thickness of said insulator layer below said gate electrode increases in steps in a direction towards said drain zone.

20. The power MOSFET according to claim 3, which further comprises a lightly doped semiconductor layer of the first conductivity type between said semiconductor substrate and said semiconductor layer of the other conductivity type.

21. The power MOSFET according to claim 1, wherein said semiconductor substrate has a layer thickness of substantially 0.2 mm.

22. The power MOSFET according to claim 20, wherein said semiconductor layer of the first conductivity type has a layer thickness of substantially 2 μ

m.

23. The power MOSFET according to claim 3, wherein said gate electrode has a layer thickness of substantially 3 μ

m.

24. The power MOSFET according to claim 23, wherein said gate electrode has a width of approximately 1 μ

m.

25. The power MOSFET according to claim 1, wherein said semiconductor layer of said second conductivity type has a layer thickness of approximately 4 μ

m.

26. The power MOSFET according to claim 1, wherein said conductive connection has a width of substantially 1 to 2 μ

m.

27. The power MOSFET according to claim 8, wherein said insulator is formed with a cavity.