Gate protection clamping circuits and techniques with controlled output discharge current
First Claim
1. A method of clamping the gate to source voltage of a FET during discharge of the FET in order to prevent oxide breakdown, the FET having a gate coupled to an output capacitor, the gate to source capacitance of the FET and the capacitance of the output capacitor forming an output capacitance, the method comprising:
- discharging the FET using a drive current until the FET is OFF;
when the FET is OFF, providing a feedback signal to reduce the drive current by at least an order of magnitude;
when the drive current is reduced, discharging the output capacitance using the drive current wherein the gate to source voltage of the FET is clamped at a pre-determined value.
3 Assignments
0 Petitions
Accused Products
Abstract
Gate protection clamping circuits and techniques with controlled output discharge current are provided. Circuits and methods according to the invention are implemented to relatively rapidly disengage single or multiple loads from a power supply without creating thermal overload. This is accomplished by first rapidly shutting OFF the power device coupling the power source to the load, and then further discharging the output capacitance with a substantially smaller, preferably regulated, current. Additional external devices may be added if faster discharge of the output capacitance is desired.
-
Citations
19 Claims
-
1. A method of clamping the gate to source voltage of a FET during discharge of the FET in order to prevent oxide breakdown, the FET having a gate coupled to an output capacitor, the gate to source capacitance of the FET and the capacitance of the output capacitor forming an output capacitance, the method comprising:
-
discharging the FET using a drive current until the FET is OFF;
when the FET is OFF, providing a feedback signal to reduce the drive current by at least an order of magnitude;
when the drive current is reduced, discharging the output capacitance using the drive current wherein the gate to source voltage of the FET is clamped at a pre-determined value. - View Dependent Claims (2, 3, 4, 5, 6)
-
-
7. A method of controlling the discharge current of an output capacitance, the output capacitance including a FET gate capacitance in a FET and a second capacitance, the method comprising:
-
discharging the FET gate capacitance using a drive current in order to shut OFF the FET and maintain the FET in an OFF state;
when the FET is OFF, providing a feedback signal based on a FET gate to source voltage, the feedback signal indicating that the FET is OFF;
reducing the drive current based on the feedback signal to provide a reduced drive current; and
discharging the second capacitance using the reduced drive current. - View Dependent Claims (8, 9, 10, 11, 12)
-
-
13. An integrated circuit for discharging an output capacitance, the output capacitance including a FET gate capacitance of a FET and a distributed board capacitance that is coupled to the FET source, the circuit comprising:
-
a controllable current source that produces a drive current, the drive current that is adapted to partially discharge the output capacitance and to shut the FET OFF;
a clamp circuit that produces a feedback signal during at least a portion of a time that the FET is OFF;
the feedback signal which reduces the drive current and, at least partially, regulates the drive current; and
wherein the gate to source voltage of the FET is maintained above a pre-determined minimum value. - View Dependent Claims (14, 15, 16, 17, 18, 19)
-
Specification