Low inductance grid array capacitor

• US 6,459,561 B1
• Filed: 06/12/2001
• Issued: 10/01/2002
• Est. Priority Date: 06/12/2001
• Status: Expired due to Fees

• Current Assignee: AVX Corporation (Kyocera Corporation)
• Original Assignee: AVX Corporation (Kyocera Corporation)
• Inventors: Korony, Gheorghe, Galvagni, John, Ritter, Andrew, Brown, Sonja
• Primary Examiner(s): Dinkins, Anthony
• Application Number:
  US09/879,803
• Time in Patent Office: 476 Days
• Field of Search: 361/303, 361/304, 361/305, 361/306.1, 361/306.3, 361/309, 361/311-313, 361/312.2, 361/328, 361/329, 361/764, 361/765, 361/766
• US Class Current: 361/306.3
• CPC Class Codes: H01G 2/065 for surface mounting, e.g. chip capacitors
• CPC Class Codes: H01G 4/232 electrically connecting two or more layers of a stacked or rolled capacitor
• CPC Class Codes: H01L 23/642 Capacitive arrangements H01L23/49589, H01L23/645, H01L23/647, H01L23/66 take precedence; capacitive effects between wiring layers on the semiconductor body H01L23/5222
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H05K 1/0231 Capacitors or dielectric substances

Abstract

An improved low inductance termination scheme is disclosed for grid array capacitors. The enhanced termination scheme provides for shorter termination length and leaves the sides of a capacitive element free from any structure. The area typically taken up by solder lands is reduced, facilitating much closer chip spacing on a circuit board. The arrangement generally includes interleaved dielectric and electrode layers in an interdigitated configuration. Vias are drilled through tabs extending from selected of the electrode layers, and then filled with suitable conductive material. Solder balls may be applied directly to this conductive material, providing a ball grid array (BGA) packaged chip ready to mount on an IC and reflow. Composition of such solder balls is easily varied to comply with specific firing conditions. Such capacitor chips are also compatible with land grid array (LGA) packaging techniques. The subject interdigitated electrode design may be utilized to form a single multilayer capacitor or multiple discrete capacitors. Such a capacitor array may be formed by retaining the external configuration and internally subdividing the electrodes. The resulting low cost, low inductance capacitor is ideal for many high frequency applications requiring decoupling capacitors.

Claims

1. A multilayer capacitor, comprising:

a body of dielectric material;

a plurality of electrode layers disposed in said body;

a plurality of electrode tabs extending from selected of said electrode layers;

a plurality of vias, said vias formed through a selected predetermined volume of said dielectric body and through selected of said tabs; and

a conductive material inserted into selected of said vias, generally filling selected said vias and providing for an electrical connection to selected of said electrode tabs.

2. A multilayer capacitor as in claim 1, wherein said plurality of electrode tabs are arranged such that selected electrode tabs extending from alternating electrode layers are vertically aligned, forming an interdigitated capacitor element.

3. A multilayer capacitor as in claim 1, wherein each of said plurality of vias is formed in selected of said electrode tabs such that each of said vias never extends through electrode tabs extending from two adjacent electrode layers.

4. A multilayer capacitor as in claim 1, wherein said body of dielectric material is characterized by a top surface and a bottom surface, and wherein said electrode layers are disposed in said dielectric body such that each said electrode layer is oriented parallel with said top surface and said bottom surface of said dielectric body.

5. A multilayer capacitor as in claim 4, wherein said conductive material is exposed on selected of said top and bottom surfaces of said dielectric body.

6. A multilayer capacitor as in claim 5, further including solder balls attached to said exposed conductive material on selected of said top and bottom surfaces of said dielectric body, forming a ball grid array capacitor.

7. A multilayer capacitor as in claim 6, further including solder balls attached to selected of said top and bottom surfaces of said dielectric body to form a distributed predetermined arrangement of solder balls over selected of said top and bottom surfaces.

8. A multilayer capacitor as in claim 5, wherein said solder balls may be composed of a variety of suitably conductive materials with a range of different melting points, thereby facilitating varied firing conditions.

9. A multilayer capacitor as in claim 1, wherein selected of said electrode layers are subdivided to provide a capacitor array of multiple discrete capacitive elements.

10. A multilayer capacitor as in claim 1, wherein said capacitor is compatible with land grid array mounting procedures for mounting said capacitor to a substrate or printed circuit board.

11. A multilayer capacitor for use in either ball grid array (BGA) or land grid array (LGA) configurations, comprising:

a plurality of electrode layers, each of said electrode layers characterized by a first and second side;

a plurality of dielectric layers wherein selected of said dielectric layers are arranged on both first and second sides of each of said electrode layers, forming a multilayer arrangement of alternating dielectric and electrode layers wherein said multilayer arrangement is characterized by a topmost layer and a bottommost layer;

a plurality of electrode tabs extending from selected of said electrode layers;

a plurality of vias defined through selected of said electrode tabs, forming hollow columns within said multilayer arrangement; and

a conductive material inserted into selected of said vias, wherein said conductive material is exposed on selected of said topmost and bottommost layers of said multilayer arrangement and wherein said conductive material provides an electrical connection to selected of said electrode tabs.

12. A multilayer capacitor as in claim 11, wherein said plurality of electrode tabs are arranged such that selected electrode tabs extending from alternating electrode layers are vertically aligned, forming an interdigitated capacitor element.

13. A multilayer capacitor as in claim 11, wherein each of said plurality of vias is formed in selected of said electrode tabs such that each of said vias never extends through electrode tabs extending from two adjacent electrode layers.

14. A multilayer capacitor as in claim 11, further including solder preforms attached to said conductive material exposed on selected of said topmost and bottommost layers of said multilayer arrangement.

15. A multilayer capacitor as in claim 14, wherein said solder preforms may be composed of a variety of suitably conductive materials with a range of different melting points, thereby facilitating varied firing conditions.

16. A multilayer capacitor as in claim 11, wherein selected of said electrode layers are subdivided to provide a capacitor array of multiple discrete capacitive elements.

17. A multilayer capacitor as in claim 11, wherein the thickness of said topmost layer and said bottommost layer may be significantly decreased relative to known multilayer capacitor configurations.

18. A multilayer capacitor array with low inductance terminations, comprising:

a plurality of dielectric layers;

a plurality of electrode layers, interleaved with selected of said dielectric layers to form a multilayered arrangement, said multilayered arrangement having a defined top surface and a defined bottom surface;

a plurality of electrode tabs extending from selected of said electrode layers;

a plurality of vias, said vias being drilled through selected predetermined locations in said layered capacitor arrangement, and each of said vias drilled through at least selected one of said electrode tabs;

a conductive material inserted into selected of said vias, generally filling selected said vias and providing for an electrical connection to selected of said corresponding electrode tabs, said conductive material forming conductive columns wherein selected ends of said conductive columns are exposed on selected of said top surface and said bottom surface of said multilayered arrangement; and

a plurality of solder balls attached to selected of said exposed ends of said conductive columns on one of either said top surface or said bottom surface of said layered capacitor arrangement.

19. A multilayer capacitor array as in claim 18, wherein said plurality of electrode tabs are arranged such that selected electrode tabs extending from alternating electrode layers are vertically aligned, forming an interdigitated capacitor element.

20. A multilayer capacitor array as in claim 18, wherein each of said plurality of vias is formed in selected of said electrode tabs such that each of said vias never extends through electrode tabs extending from two adjacent electrode layers.

21. A multilayer capacitor as in claim 18, wherein said plurality of solder balls may be composed of a variety of suitably conductive materials with a range of different melting points, thereby facilitating varied firing conditions.

22. A multilayer capacitor array as in claim 18, wherein selected of said electrode layers are subdivided to provide multiple discrete capacitive elements.

23. A multilayer capacitor array as in claim 21, further including solder balls attached to selected of said top and bottom surfaces of said dielectric body to form a predetermined distributed arrangement of solder balls over selected of said top and bottom surfaces.