Self referencing 1T/1C ferroelectric random access memory

• US 6,459,609 B1
• Filed: 12/13/2001
• Issued: 10/01/2002
• Est. Priority Date: 12/13/2001
• Status: Expired due to Term

• Current Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Original Assignee: Ramtron International Corporation (Infineon Technologies AG)
• Inventors: Du, Xiao Hong
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): LE, TOAN K
• Application Number:
  US10/022,119
• Time in Patent Office: 292 Days
• Field of Search: 365/145, 365/149, 365/189.07, 365/207
• US Class Current: 365/145
• CPC Class Codes: G11C 11/22 using ferroelectric elements

Abstract

An implementation of 1T/1C nonvolatile ferroelectric RAMS without using any reference cells—the polarization state in a memory cell is determined by applying two consecutive plate pulses on the ferroelectric capacitor in the memory cell, preamplifying the bit line voltages corresponding to these two plate pulses, and comparing the preamplified voltages. The two consecutive plate pulses have the same polarity.

Claims

1. A self-referencing read circuit for a 1T/1C ferroelectric memory comprising:

a ferroelectric memory, cell coupled to a plate line and a bit line, the bit line having an associated bit line capacitance;

a load capacitor;

means for selectively coupling the load capacitor to the bit line;

a preamplifier having an input coupled to the bit line and an output;

means for sampling a first preamplifier output voltage during the application of a first plate line pulse.;

means for sampling a second preamplifier output voltage during the application of a second plate line pulse; and

a sense amplifier for comparing the first and second preamplifier output voltages to provide a data output signal.

2. The read circuit of claim 1 in which the ferroelectric memory cell comprises a ferroelectric capacitor in series with a transistor.

3. The read circuit of claim 1 in which the means for sampling a first preamplifier output voltage comprises a capacitor in series with a switch device such as a transistor or a transmission gate.

4. The read circuit of claim 1 in which the means for selectively coupling the load capacitor to the bit line comprises a capacitor in series with a switch device such as a transistor or a transmission gate.

5. The read circuit of claim 1 in which the means for sampling a second preamplifier output voltage comprises a capacitor in series with a switch device such as transistor or a transmission gate.

6. A method of reading a 1T/1C ferroelectric memory comprising

coupling a load capacitor to a bit line;

precharge the bit line and the load capacitor to ground;

transferring charge from a 1T/1C memory cell to the bit line to create a first bit line voltage;

preamplifying the first bit line voltage to create a first output voltage;

storing the first output voltage;

decoupling the load capacitor from the bit line;

precharge the bit line to ground;

transferring charge from the 1T/1C memory cell to the bit line to create a second bit line voltage;

preamplifying the second bit line voltage to create a second output voltage;

storing the second output voltage; and

comparing the first and second output voltages to provide a logic output signal.

7. The method of claim 6 further comprising sizing the load capacitor such that the first output voltage is less than the second output voltage when the 1T/1C memory cell has an initial upward polarization.

8. A method of determining a polarization state in a 1T/1C ferroelectric memory cell coupled to a bit line comprising:

applying two consecutive plate line pulses to a ferroelectric capacitor in the 1T/1C memory cell;

preamplifying bit line voltages corresponding to the two plate line pulses; and

comparing the magnitude of the preamplified bit line voltages to determine the polarization state of the 1T/1C ferroelectric memory cell.

9. The method of claim 8 in which applying two consecutive plate line pulses comprises applying two consecutive plate line pulses of the same polarity.

10. The method of claim 8 in which preamplifying bit line voltages comprises preamplifying two consecutive bit line voltage pulses using one signal path per bit line.

11. The method of claim 8 further comprising adding additional capacitance to the bit line during the first plate line pulse.

12. A self-referencing read circuit for a 1T/1C ferroelectric memory comprising:

an array of ferroelectric memory cells coupled to respective plate lines, bit lines, and word lines;

a plurality of controlled load capacitors, wherein a single load capacitor is associated with each bit line;

a plurality of preamplifiers, each having an input coupled to the respective bit line;

a first set of capacitors for sampling a first set of preamplifier output voltages during the application of a first plate line pulse;

a second set of capacitors for sampling a second set of preamplifier output voltages during the application of a second plate line pulse; and

a plurality of sense amplifiers for comparing the first and second sets of preamplifier output voltages to provide a plurality of data output signals corresponding to the data in a subset of the array of 1T/1C ferroelectric memory cells.

13. The read circuit of claim 12 in which each sense amplifier further comprises two input/outputs that are capacitively balanced.

14. The read circuit of claim 12 in which preamplifying bit line voltages comprises preamplifying two consecutive bit line voltage pulses using one signal path per bit line.

15. The read circuit of claim 12 in which preamplifying bit line voltages comprises preamplifying two consecutive bit line voltage pulses using an analogue amplifier with a single-ended input.

16. The read circuit of claim 12 in which each preamplifier comprises a high impedance input preamplifier for isolating each sense amplifier from the respective bit line.

17. The read circuit of claim 12 further comprising a driver circuit for driving each of the plate lines.

18. The read circuit of claim 12 further comprising a driver circuit for driving each of the word lines.

19. The read circuit of claim 12 in which the load capacitor is about 60% of the bit line capacitance .

20. The read circuit of claim 12 in which the bit line capacitance is about 0.42 pF.

21. The read circuit of claim 12 in which the capacitance of each capacitor in the first set of capacitors is about 0.04 pF.

22. The read circuit of claim 12 in which the capacitance of each capacitor in the second set of capacitors is about 0.04 pF.