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SEMICONDUCTOR-ON-INSULATOR TRANSISTOR, MEMORY CIRCUITRY EMPLOYING SEMICONDUCTOR-ON-INSULATOR TRANSISTORS, METHOD OF FORMING A SEMICONDUCTOR-ON-INSULATOR TRANSISTOR, AND METHOD OF FORMING MEMORY CIRCUITRY EMPLOYING SEMICONDUCTOR-ON-INSULATOR TRANSISTORS

  • US 6,459,610 B1
  • Filed: 04/14/1999
  • Issued: 10/01/2002
  • Est. Priority Date: 06/21/1996
  • Status: Expired due to Term
First Claim
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1. Memory circuitry comprising a plurality of memory cells not requiring sequential access, at least a portion of the plurality having more than two memory cells for a single bit line contact, said portion of memory cells further comprising individual source regions and a common shared drain region, the source regions being disposed elevationally over the common shared drain region, and transistors of said portion of memory cells further comprising silicon-on-insulator field effect transistors.

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