Nonvolatile semiconductor memory and automatic erasing/writing method thereof

• US 6,459,640 B1
• Filed: 08/17/2001
• Issued: 10/01/2002
• Est. Priority Date: 02/01/2001
• Status: Expired due to Term

• Current Assignee: Renesas System Design, Co., Ltd. (Renesas Electronics Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation), Mitsubshi Electric Engineering Company Limited (Mitsubishi Electric Corporation), Mitsubishi Electric Semiconductor Software Company Limited
• Inventors: Tanaka, Tsutomu, Kimura, Hiroyuki, Tani, Kunio, Iba, Tomohisa, Tashiro, Tetsu, Sezaki, Toshihiro, Hongo, Katsunobu, Kamiya, Mikio
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): LE, THONG QUOC
• Application Number:
  US09/931,243
• Publication Number:
  US 20020101764A1
• Time in Patent Office: 410 Days
• Field of Search: 365/185.29, 365/218, 365/200, 365/230.03, 365/230.06, 365/240, 365/189.04
• US Class Current: 365/218
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/22 Safety or protection circuits preventing unauthorised or accidental access to memory cells
• CPC Class Codes: G11C 29/846 by choosing redundant lines at an output stage

Abstract

A nonvolatile semiconductor memory includes a memory block composed of a memory array having a plurality of memory cells arranged in a matrix form, each of the memory cells being composed of a nonvolatile transistor; a memory decoder necessary for erasing/writing/reading data of the nonvolatile transistor in the memory array; a charge pump necessary for erasing/writing/reading the data of the nonvolatile transistor in the memory array; a register having each of a plurality of control signals for controlling the memory decoder and the charge pump allocated to register 1 bit; and an updating device for updating a content of the register by a data processor coupled to the register. By using this updating device to update the content of the register, the memory decoder and the charge pump are controlled, the data of the memory block is erased, and data is written in/read from the nonvolatile transistor. Thus a selecting device other than a laser can be applied for suppressing the increase of an LSI circuit size in the same chip as that for a dedicated control circuit, verifying the disconnected state of a FUSE circuit in the memory, and trimming the FUSE circuit.

Claims

1. A nonvolatile semiconductor memory comprising:

a memory block composed of a memory array having a plurality of memory cells arranged in a matrix form, each of the memory cells being composed of a nonvolatile transistor;

a memory decoder necessary for erasing/writing/reading data of the nonvolatile transistor in the memory array;

a charge pump necessary for erasing/writing/reading the data of the nonvolatile transistor in the memory array;

a register having each of a plurality of control signals for controlling the memory decoder and the charge pump allocated to register 1 bit;

means for updating a content of the register by a data processor coupled to the register; and

means for controlling the memory decoder and the charge pump by a trigger signal from the data processor.

2. The nonvolatile semiconductor memory according to claim 1, further comprising:

means for erasing data of the memory block by updating the content of the register.

3. The nonvolatile semiconductor memory according to claim 1, further comprising:

means for writing data in the nonvolatile transistor in the memory block by updating the content of the register.

4. The nonvolatile semiconductor memory according to claim 1, further comprising:

means for reading data from the nonvolatile transistor in the memory block by updating the content of the register.

5. An automatic erasing method of a nonvolatile semiconductor memory, the nonvolatile semiconductor memory including:

a memory block composed of a memory array having a plurality of memory cells arranged in a matrix form, each of the memory cells being composed of a nonvolatile transistor;

a memory decoder necessary for erasing/writing/reading data of the nonvolatile transistor in the memory array;

a charge pump necessary for erasing/writing/reading the data of the nonvolatile transistor in the memory array;

a register having each of a plurality of control signals for controlling the memory decoder and the charge pump allocated to register 1 bit; and

means for updating a content of the register by a data processor coupled to the register, and

the automatic erasing method comprising the step of;

erasing data of the memory block by using the updating means to input a trigger signal from the data processor to the register.

6. An automatic writing method of a nonvolatile semiconductor memory, the nonvolatile semiconductor memory including:

a memory block composed of a memory array having a plurality of memory cells arranged in a matrix form, each of the memory cells being composed of a nonvolatile transistor;

a memory decoder necessary for erasing/writing/reading data of the nonvolatile transistor in the memory array;

a charge pump necessary for erasing/writing/reading the data of the nonvolatile transistor in the memory array;

a register having each of a plurality of control signals for controlling the memory decoder and the charge pump allocated to register 1 bit; and

means for updating a content of the register by a data processor coupled to the register, and

the automatic writing method comprising the step of;

writing data in the nonvolatile transistor in the memory block by using the updating means to input a trigger signal from the data processor to the register.

7. A nonvolatile semiconductor memory comprising:

a memory block composed of a memory array having a plurality of memory cells arranged in a matrix form, each of the memory cells being composed of a nonvolatile transistor;

a dummy memory array for replacing the memory array;

first means for replacing one memory array in the memory block by the dummy memory array, by executing trimming processing;

second means for replacing one memory array in the memory block by the dummy memory array, by setting data in a dummy register, without using a replacing circuit including the dummy memory array; and

means for replacing the memory array by the dummy memory array carried out by the first means, by the second means.

8. The nonvolatile semiconductor memory according to claim 7, further comprising;

means for giving priority to the replacement by the first means even if replacement processing by the second means has been set, when one memory array in the memory block is replaced by the dummy memory array by the first means.

9. The nonvolatile semiconductor memory according to claim 7, further comprising:

means for reading information regarding the replacement of one memory array in the memory block by the dummy memory array by the first means, and information regarding the replacement processing by the second means, and comparing these bits of information with each other.

10. The nonvolatile semiconductor memory according to claim 7, further comprising:

means for writing a dummy register value set by the replacement processing of the second means in the memory cell composed of the nonvolatile transistor, and then reading the dummy register value; and

means for reading bits of information regarding the replacement processing by the first and second means, and comparing these bits of information with each other.