Multi-pair gigabit ethernet transceiver

• US 6,459,746 B2
• Filed: 02/09/2001
• Issued: 10/01/2002
• Est. Priority Date: 11/09/1998
• Status: Expired due to Term

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Kruse, David E., Hatamian, Mehdi, Creigh, John L., Agazzi, Oscar E., Samueli, Henry, Abnous, Arthur
• Primary Examiner(s): CORRIELUS, JEAN B
• Application Number:
  US09/781,914
• Publication Number:
  US 20010055331A1
• Time in Patent Office: 599 Days
• Field of Search: 375/254, 375/259, 375/260, 375/285, 375/296, 375/355, 375/356, 375/371, 375/377, 375/233, 375/326, 375/346, 375/349, 375/354, 375/242, 370/503, 370/507, 370/516, 370/357, 370/299, 370/458, 331/2, 331/11, 331/18, 331/46, 331/56, 331/107.P, 327/141, 327/147, 327/144, 382/2, 360/46, 342/201
• US Class Current: 375/371
• CPC Class Codes: G01R 31/3004 Current or voltage test
• CPC Class Codes: G01R 31/3008 Quiescent current [IDDQ] test or leakage current test
• CPC Class Codes: G01R 31/3016 Delay or race condition test, e.g. race hazard test
• CPC Class Codes: G01R 31/31715 Testing of input or output circuits; test of circuitry between the I/C pins and the functional core, e.g. testing of input or output driver, receiver, buffer
• CPC Class Codes: G01R 31/318502 Test of Combinational circuits
• CPC Class Codes: G01R 31/318552 Clock circuits details
• CPC Class Codes: G01R 31/318594 Timing aspects clock circuits G01R31/318552
• CPC Class Codes: H04B 3/23 using a replica of transmitted signal in the time domain, e.g. echo cancellers
• CPC Class Codes: H04B 3/235 combined with adaptive equaliser
• CPC Class Codes: H04B 3/32 Reducing cross-talk, e.g. by compensating
• CPC Class Codes: H04L 1/0021 in which the algorithm uses adaptive thresholds
• CPC Class Codes: H04L 1/0047 Decoding adapted to other signal detection operation in conjunction with sequence estimation or equalization H04L25/03286
• CPC Class Codes: H04L 1/0053 specially adapted for power saving
• CPC Class Codes: H04L 1/0054 Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms
• CPC Class Codes: H04L 1/0059 Convolutional codes
• CPC Class Codes: H04L 1/006 Trellis-coded modulation
• CPC Class Codes: H04L 1/242 by comparing a transmitted test signal with a locally generated replica
• CPC Class Codes: H04L 2001/0096 Channel splitting in point-to-point links
• CPC Class Codes: H04L 2025/03363 Multilevel H04L2025/03369 takes precedence
• CPC Class Codes: H04L 2025/03369 Partial response
• CPC Class Codes: H04L 2025/03477 : not time-recursive
• CPC Class Codes: H04L 2025/0349 : as a feedback filter
• CPC Class Codes: H04L 2025/03496 : as a prediction filter
• CPC Class Codes: H04L 2025/03503 : as a combination of feedback and prediction filters
• CPC Class Codes: H04L 2025/03617 : Time recursive algorithms H04L2025/03643 takes precedence
• CPC Class Codes: H04L 2025/03745 : Timing of adaptation
• CPC Class Codes: H04L 25/03038 : with a non-recursive structure H04L25/03031 takes precedence
• CPC Class Codes: H04L 25/03057 : with a recursive structure H04L25/03031 takes precedence
• CPC Class Codes: H04L 25/03146 : with a recursive structure H04L25/03127 takes precedence
• CPC Class Codes: H04L 25/03197 : methods of calculation involving metrics
• CPC Class Codes: H04L 25/03203 : Trellis search techniques
• CPC Class Codes: H04L 25/03235 : with state-reduction using feedback filtering
• CPC Class Codes: H04L 25/03267 : with decision feedback equalisers
• CPC Class Codes: H04L 25/03987 : Equalisation for sparse channels
• CPC Class Codes: H04L 25/067 : providing soft decisions, i.e. decisions together with an estimate of reliability H04L25/068 and H04L25/069 take precedence; sequence estimation techniques H04L25/03178
• CPC Class Codes: H04L 25/14 : Channel dividing arrangements , i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver
• CPC Class Codes: H04L 25/4917 : using multilevel codes
• CPC Class Codes: H04L 25/497 : by correlative coding, e.g. partial response coding or echo modulation coding transmitters and receivers for partial response systems transversal equalizers at the transmitter end H04L25/03343
• CPC Class Codes: H04L 7/0062 : detection of error based on data decision error, e.g. Mueller type detection
• CPC Class Codes: H04L 7/0334 : Processing of samples having at least three levels, e.g. soft decisions

Abstract

Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitter'"'"'s partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow. A receive clock signal is generated such that it is synchronous in frequency with analog sampling clock signals and has a particular phase offset with respect to one of the sampling clock signals. This phase offset is adjusted such that system performance degradation due to coupling of switching noise from the digital sections to the analog sections is substantially minimized.

Claims

1. A method for reducing system performance degradation due to switching noise in a system, the system comprising a set of subsystems, each of the subsystems comprising an analog section and a digital section, each of the analog sections operating in accordance with a corresponding one of a set of sampling clock signals, the sampling clock signals being synchronous in frequency, the digital sections operating in accordance with a receive clock signal, the method comprising the operations of:

generating the receive clock signal such that the receive clock signal is synchronous in frequency with the sampling clock signals and having a phase offset with respect to one of the sampling clock signals; and

adjusting the phase offset such that system performance degradation due to coupling of switching noise from the digital sections to the analog sections is substantially minimized.

2. The method of claim 1 further comprising the operation of:

adjusting a sampling phase of at least one of the sampling clock signals such that a subsystem performance error of the subsystem which corresponds to said one of the sampling clock signals is substantially minimized.

3. The method of claim 1 further comprising the operation of:

adjusting a sampling phase of each of the sampling clock signals such that a subsystem performance error of a corresponding subsystem is substantially minimized.

4. A method for reducing effect of switching noise in a system, the system comprising a set of subsystems, each of the subsystems comprising an analog section and a digital section, each of the analog sections operating in accordance with a corresponding one of a set of sampling clock signals, the digital sections operating in accordance with a receive clock signal, the method comprising the operations of:

generating the sampling clock signals such that the sampling clock signals are synchronous in frequency with each other;

generating the receive clock signal such that the receive clock signal is synchronous in frequency with the sampling clock signals and having a phase offset with respect to one of the sampling clock signals; and

adjusting the phase offset such that effect of switching noise from the digital sections on the analog sections is substantially minimized.

5. The method of claim 4 further comprising the operation of:

adjusting a phase of at least one of the sampling clock signals such that a subsystem performance error of the subsystem which corresponds to said one of the sampling clock signals is substantially minimized.

6. The method of claim 4 wherein the operation of generating the sampling clock signals comprises the operations of:

(a) generating a phase error for each of the sampling clock signals from a corresponding phase detector;

(b) inputting each of the phase errors to a corresponding loop filter;

(c) generating filtered phase errors from the corresponding loop filters;

(d) inputting each of the filtered phase errors to a corresponding oscillator;

(e) generating phase control signals from the corresponding oscillators;

(f) inputting each of the phase control signals to a corresponding phase selector; and

(g) generating the sampling clock signals from the corresponding phase selectors.

7. The method of claim 6 wherein the operation of generating the receive clock signal comprises the operations of:

(1) combining one of the phase control signals with the phase offset to produce a phase shift value;

(2) inputting the phase shift value to a receive clock phase selector; and

(3) generating the receive clock signal from the receive clock phase selector.

8. The method of claim 7 wherein the phase shift value comprises a set of phase steps and wherein operation (2) comprises the operation of inputting the phase steps consecutively to the receive clock phase selector.

9. The method of claim 7 wherein the operation of adjusting the phase offset of the receive clock comprises the operations of:

(4) determining a set of phase offset values for the phase offset;

(5) computing a set of system performance errors corresponding one-to-one to the phase offset values; and

(6) selecting one of the phase offset values, said one phase offset value corresponding to a minimum of the system performance errors.

10. The method of claim 9 wherein the set of phase offset values comprises 64 phase offset values.

11. The method of claim 9 wherein operation (5) comprises the operations of:

computing a subsystem performance error for each of the subsystems for one of the phase offset values;

combining the subsystem performance errors to generate the corresponding system performance error.

12. The method of claim 11 wherein the operation of computing a subsystem performance error for a corresponding subsystem comprises:

squaring a slicer error associated with the subsystem;

accumulating a number of associated squared slicer errors via a filter for a period of time; and

outputting an accumulated squared error as the corresponding subsystem performance error after the period of time.

13. The method of claim 6 wherein, in operation (a), each of the phase detectors receives a corresponding slicer error and a corresponding tentative decision from a decoding system.

14. The method of claim 13 wherein operation (a) comprises:

(1) generating a pre-cursor phase error by multiplying the corresponding tentative decision by a delayed version of the corresponding slicer error;

(2) generating a post-cursor phase error by multiplying the corresponding slicer error by a delayed version of the corresponding tentative decision; and

(3) combining the pre-cursor and post-cursor phase errors to produce the corresponding phase error.

15. The method of claim 14 wherein operations (1), (2) and (3) are performed via a lattice structure, the lattice structure comprising two delay elements, two multipliers and an adder.

16. The method of claim 15 wherein operation (3) includes the operation of combining the pre-cursor, post-cursor phase errors and an offset input from a control unit to produce the corresponding phase error.

17. The method of claim 6 wherein operation (c) comprises:

accumulating a number of consecutive values of one of the phase errors via a first filter, resulting in a sum value;

outputting the sum value from the first filter;

integrating the sum value via a second filter to produce an integral value; and

combining the sum value and the integral value to produce a filtered phase error.

18. The method of claim 17 wherein operation (3) includes the operation of scaling the integrated sum value by a scale factor to produce the integral value.

19. The method of claim 17 wherein operation (c) further comprises, before operation (3), the operation of multiplying the sum value by a factor different than 1 when the system is operating in a different bandwidth mode.

20. The method of claim 6 wherein operation (e) comprises the operation of filtering recursively the filtered phase errors to produce the corresponding phase control signals.

21. The method of claim 20 wherein operation (e) further comprises the operation of scaling, before filtering recursively, the filtered phase errors by a scale factor.

22. The method of claim 6 wherein operation (g) comprises the operations of:

inputting a multi-phase input signal from a clock generator to each of the phase selectors; and

selecting at each of the phase selectors one of the phases of the multi-phase input signal based on the phase control signal received from the corresponding oscillator.