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Multi-pair gigabit ethernet transceiver

  • US 6,459,746 B2
  • Filed: 02/09/2001
  • Issued: 10/01/2002
  • Est. Priority Date: 11/09/1998
  • Status: Expired due to Term
First Claim
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1. A method for reducing system performance degradation due to switching noise in a system, the system comprising a set of subsystems, each of the subsystems comprising an analog section and a digital section, each of the analog sections operating in accordance with a corresponding one of a set of sampling clock signals, the sampling clock signals being synchronous in frequency, the digital sections operating in accordance with a receive clock signal, the method comprising the operations of:

  • generating the receive clock signal such that the receive clock signal is synchronous in frequency with the sampling clock signals and having a phase offset with respect to one of the sampling clock signals; and

    adjusting the phase offset such that system performance degradation due to coupling of switching noise from the digital sections to the analog sections is substantially minimized.

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