DC offset correction loop for radio receiver

• US 6,459,889 B1
• Filed: 02/29/2000
• Issued: 10/01/2002
• Est. Priority Date: 02/29/2000
• Status: Active Grant

• Current Assignee: Motorola Solutions, Inc.
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Ruelke, Charles R.
• Primary Examiner(s): Chin, Vivian
• Assistant Examiner(s): SHARMA, SUJATHA R
• Application Number:
  US09/515,288
• Time in Patent Office: 945 Days
• Field of Search: 455/324, 455/296, 455/310, 455/232.1, 455/234.1, 455/234.2, 455/239.1, 455/303, 341/118, 341/155, 330/129, 330/141, 330/279, 330/281, 330/278
• US Class Current: 455/296
• CPC Class Codes: H04B 1/30 for homodyne or synchrodyne receivers demodulator circuits H03D1/22

Abstract

A receiver direct current offset correction loop (DCOCL) circuit digitizes the baseband analog control voltage (148) using an Analog-to-Digital Converter (ADC) block 160, which is then processed at control block (162) to drive compensation circuitry 164 in a classic feedback configuration. The DCOCL is augmented by an independent automatic gain control (AGC) circuit that utilizes the same control signal (148). The AGC circuit includes a multiplicity of adjustable gain stages (114, 118, 158) with threshold and characteristic response that is controlled by AGC control block (122). Both the AGC and DCOCL circuits are dynamically configured for optimum complimentary operation via the microprocessor (236) depending on the receiver'"'"'s operating environment and protocol requirements. Subsequent direct current (DC) voltage drift is detected by the digital signal processor (DSP) block (230) which in turn flags the microprocessor to reinitiate the correction sequence when needed. Subsequent to the microprocessor controlled hardware correction sequence, the DSP digitally equalizes any remaining offset errors in the recovered data through a multiplicity of compensation algorithms optimized to specific operating environments. This provides for optimum correction of the baseband DC offsets with minimal degradation of receiver performance.

Claims

1. A method of compensating for DC offset in a radio receiver, comprising:

determining an initial DC offset of the receiver;

implementing an initial DC offset correction to determine a DC offset correction value and produce a corrected DC offset;

holding the DC offset correction value at a fixed value;

determining the need to re-correct the DC offset of the receiver;

determining an operational mode of the receiver; and

implementing a DC offset correction using a technique compatible with the operational mode of the radio receiver, the technique being selected from one of a plurality of possible techniques.

2. The method of compensating DC offset in a radio receiver in accordance with claim 1, wherein the determining an operational mode of the receiver comprises determining if the receiver is operating under a slotted protocol or a non-slotted protocol.

3. The method of compensating DC offset in a radio receiver in accordance with claim 2, wherein if the receiver is operating in a non-slotted protocol, then implementing the DC offset correction is delayed until the receiver is receiving no on-channel carrier.

4. The method of compensating DC offset in a radio receiver in accordance with claim 2, wherein if the radio receiver is operating using a non-slotted protocol, then implementing the DC correction comprises:

setting an AGC to a value which eliminates on-channel input signals;

carrying out a DC offset correction process; and

restoring normal AGC operation.

5. The method of compensating DC offset in a radio receiver in accordance with claim 2, wherein if the receiver is operating in a slotted protocol the method further comprises determining if an on-channel carrier cycles on and off under the slotted protocol.

6. The method of compensating DC offset in a radio receiver in accordance with claim 5, wherein if the slotted protocol cycles an on-channel carrier on and off, then implementing the DC offset correction is delayed until the on-channel carrier is cycled off and any off-channel carrier is attenuated.

7. The method of compensating DC offset in a radio receiver in accordance with claim 5, wherein if the protocol does not cycle the on-channel carrier on and off, then the on channel carrier is attenuated to a negligible value before implementing the DC offset correction.

8. The method of compensating DC offset in a radio receiver in accordance with claim 1, wherein determining the need to re-correct the DC offset of the receiver comprises determining if an average DC offset is greater than a threshold.

9. The method of compensating DC offset in a radio receiver in accordance with claim 8, wherein the average DC offset is computed by a technique selected in accordance with the operational protocol of the radio receiver.

10. The method of compensating DC offset in a radio receiver in accordance with claim 8, wherein the average DC offset is calculated by one or more techniques selected from simple integration, envelope averaging, slotted time averaging and weighted averaging.

11. The method of compensating DC offset in a radio receiver in accordance with claim 1, wherein if the radio receiver is operating using a slotted protocol, then implementing the DC offset correction comprises:

presetting a DC offset correction; and

allowing an AGC loop to respond while a DC offset correction loop corrects the DC offset.

12. An apparatus for compensating DC offset in a radio receiver, comprising:

an automatic gain control (AGC) loop;

a DC offset correction loop nested within the AGC loop;

a controller which implements a DC offset correction sequence according to an operational protocol of the radio receiver, wherein;

if the radio receiver is operating using a non-slotted protocol, the DC offset correction sequence comprises;

presetting a DC offset correction; and

allowing the AGC loop to respond while the DC offset correction loop corrects the DC offset;

and wherein;

if the radio receiver is operating using a slotted protocol, the DC correction sequence comprises;

setting the AGC to a value which eliminates on-channel input signals;

carrying out a DC offset correction process; and

restoring normal AGC operation.

13. An apparatus for compensating DC offset in a radio receiver, comprising:

an automatic gain control (AGC) loop;

a DC offset correction loop nested within the AGC loop;

a controller which implements a first DC offset correction sequence in the event the radio is operating according to a non-slotted protocol, and implements a second DC offset correction sequence in the event the radio is operating according to a slotted protocol.

14. The apparatus for compensating DC offset in a radio receiver in accordance with claim 13, wherein if the radio receiver is operating using a non-slotted protocol, the first DC offset correction sequence comprises:

presetting a DC offset correction; and

allowing the AGC loop to respond while the DC offset correction loop corrects the DC offset.

15. The apparatus for compensating DC offset in a radio receiver in accordance with claim 13, wherein if the radio receiver is operating using a slotted protocol, the second DC correction sequence comprises:

setting the AGC to a value which eliminates on-channel input signals;

carrying out a DC offset correction process; and

restoring normal AGC operation.

16. The apparatus for compensating DC offset in a radio receiver in accordance with claim 13 further comprising a digital signal processor which computes an average DC offset using one or more techniques selected from simple integration, envelope averaging, slotted time averaging and weighted averaging.

17. The apparatus for compensating DC offset in a radio receiver in accordance with claim 16, wherein the average DC offset value is represented by a multi-bit digital signal having a least significant bit, and wherein the threshold is selected to be two times the DC value represented by the signal'"'"'s least significant bit.

18. The apparatus for compensating DC offset in a radio receiver in accordance with claim 13, further comprising a digital signal processor which computes an average DC offset;

and

wherein the controller implements one of the first and second DC offset correction sequences when the average DC offset exceeds a threshold.

19. A method for compensating DC offset in a radio receiver which operates using a non-slotted communication protocol, comprising:

providing an automatic gain control (AGC) loop;

providing a DC offset correction loop nested within the AGC loop;

implementing a DC offset correction sequence which comprises;

presetting a DC offset correction; and

allowing the AGC loop to respond while the DC offset correction loop corrects the DC offset.

20. A method for compensating DC offset in a radio receiver which operates using a slotted communication protocol, comprising:

providing an automatic gain control (AGC) loop;

providing a DC offset correction loop nested within the AGC loop;

implementing a DC offset correction sequence which comprises;

setting the AGC to a value which eliminates on-channel input signals;

carrying out a DC offset correction process; and

restoring normal AGC operation.

21. An apparatus for compensating DC offset in a radio receiver which operates using a non-slotted communication protocol, comprising:

an automatic gain control (AGC) loop;

a DC offset correction loop nested within the AGC loop;

a controller which implements a DC offset correction sequence, the sequence comprising;

presetting a DC offset correction; and

allowing the AGC loop to respond while the DC offset correction loop corrects the DC offset.

22. An apparatus for compensating DC offset in a radio receiver which operates using a slotted communication protocol, comprising:

an automatic gain control (AGC) loop;

a DC offset correction loop nested within the AGC loop;

a controller which implements a DC offset correction sequence, the sequence comprising;

setting the AGC to a value which eliminates on-channel input signals;

carrying out a DC offset correction process; and

restoring normal AGC operation.