Routing program method for positioning unit pins in a hierarchically designed VLSI chip

• US 6,460,169 B1
• Filed: 10/21/1999
• Issued: 10/01/2002
• Est. Priority Date: 10/21/1999
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Smith, Howard H., Camporese, Peter J., Dansky, Allan H.
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): Whitmore, Stacy
• Application Number:
  US09/422,040
• Time in Patent Office: 1,076 Days
• Field of Search: 716/2, 716/9, 716/10, 716/11, 716/13
• US Class Current: 716/122
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence

Abstract

A routing program length method for positioning unit pins in a hierarchically designed VLSI chip first identifies unit pin positions initially assigned in a hierarchical VLSI design that, if implemented, would increase the net length of the net of which the unit pins are a part. To identify unit pins, where the unit pin position assigned by the unit designer turns out to be a poor choice of position when the unit is integrated into the top level design, a “flat” file is created of the completed VLSI design with the units positioned on the chip, including their pin placements as assigned by the unit designers. The flat file includes not only top level unit data and unit-to-unit net data, but also macro data and macro net data integral to each unit design. The flat design data file is used to generate two pin logs; one pin log includes the Incremental lengths of each net including the incremental lengths associated with the unit pins (if any) assigned by the designers of the units. The other pin log is the same, except it does not include the unit pins and the incremental net length associated with the unit pins. A commercially available program, for example, a Minimum Spanning Tree (MST) program or a Steiner Minimal Tree program is run against every net; once against the nets in the pin log list that includes the pins assigned by the designers of the units, and once against the nets in the pin log list that does not include assigned unit pins. The output of interest of the MST (or similar program) run against the net files with and without pin assignments is a text file containing the net names, number of pins per net with and without unit pins and the difference between the net lengths with and without unit pin assignments. If the difference exceeds a threshold value a router program is run in isolation against each net without unit pins. Pins are placed where the wiring route for the net crosses each unit boundary.

Claims

1. A method for positioning of unit pins in a VLSI design, including the steps of:

(a) identifying, in a VLSI chip design, external nets with unit pins located in a sub-optimal position with respect to minimum net length, by;

determining a minimal net length for any external net with unit pins assigned;

determining a minimal net length for an external net without unit pins assigned;

calculating a difference between said minimal net length for an external net with unit pins assigned and said minimal net length for an external net without unit pins assigned;

identifying as an external net with unit pins in a sub-optimal position, units nets where said differences exceeds a threshold;

(b) running a routing program on each external net identified in the identifying step positioning unit pins for said net in accordance with where the minimal line crosses a unit boundary;

(c) positioning unit pins for said net in accordance with where the wire route crosses a unit boundary.

3. A method for positioning of unit pins in a VLSI design as in claim 1 including the further step of displaying, in isolation, each external net identified in said identifying step.

5. A method for positioning of unit pins in a VLSI design as in claim 1 wherein said step of determining a minimal net length for external nets with unit pins assigned and said step of determining minimal net length for external nets without unit pins assigned runs a minimum spanning tree program against external nets with unit pins assigned and against external nets without unit pins assigned.

7. A method for positioning of unit pins in a VLSI design as in claim 1 wherein said step of determining a minimal net length for external nets with unit pins assigned and said step of determining minimal net length for external nets without unit pins assigned runs a Steiner minimal tree program against external nets with unit pins assigned and against external nets without unit pins assigned.

2. A method for positioning of unit pins in a VLSI design, including the steps of:

(a) identifying, in a VLSI chip design, external nets with unit pins located in a sub-optimal position with respect to minimum net length, by;

generating a flat data file that includes internal nets and external nets including macro pin positions and unit pin positions referenced to a common coordinate system;

determining a minimal net length for any external net with unit pins assigned;

determining a minimal net length for an external net without unit pins assigned;

calculating a difference between said minimal net length for an external net with unit pins assigned and said minimal net length for an external net without unit pins assigned;

identifying as an external net with unit pins in a sub-optimal position, units nets where said differences exceeds a threshold;

(b) running a routing program on each external net identified in the identifying step positioning unit pins for said net in accordance with where the minimal line crosses a unit boundary;

(c) positioning unit pins for said net in accordance with where the wire route crosses a unit boundary.

4. A method for positioning of unit pins in a VLSI design as in claim 2 including the further step of displaying, in isolation, each external net identified in said identifying step.

6. A method for positioning of unit pins in a VLSI design as in claim 2 wherein said step of determining a minimal net length for external nets with unit pins assigned and said step of determining minimal net length for external nets without unit pins assigned runs a minimum spanning tree program against external nets with unit pins assigned and against external nets without unit pins assigned.

8. A method for positioning of unit pins in a VLSI design as in claim 2 wherein said step of determining a minimal net length for external nets with unit pins assigned and said step of determining minimal net length for external nets without unit pins assigned runs a Steiner minimal tree program against external nets with unit pins assigned and against external nets without unit pins assigned.

9. A method for positioning of unit pins in a VLSI design as in claim 2 wherein said generating step includes assigning the top level net name to internal unit nets that are connected to unit pins and that are part of the named net.

10. A method for positioning of unit pins in a VLSI design as in claim 2 wherein said generating step includes converting unit pin coordinates and macro pin coordinates to a common top level coordinate system.

11. A method for positioning of unit pins in a VLSI design as in claim 2 wherein said generating step includes assigning the top level net name to internal unit nets that are connected to unit pins and that are part of the named net;

and converting unit pin coordinates and macro pin coordinates to a common top level coordinate system.