Method of forming micromachined sealed capacitive pressure sensors

• US 6,460,234 B1
• Filed: 05/12/2000
• Issued: 10/08/2002
• Est. Priority Date: 08/19/1998
• Status: Expired due to Term

• Current Assignee: Wisconsin Alumni Research Foundation (University of Wisconsin System)
• Original Assignee: Wisconsin Alumni Research Foundation (University of Wisconsin System)
• Inventors: Gianchandani, Yogesh B.
• Primary Examiner(s): Arbes, Carl J.
• Assistant Examiner(s): TRINH, MINH N
• Application Number:
  US09/570,736
• Time in Patent Office: 879 Days
• Field of Search: 29/253.5, 29/254.2, 296/211, 295/95, 295/921, 737/18, 737/20, 737/21, 737/26, 737/24, 438/456, 438/700, 216/2, 216/24, 216/33, 216/39
• US Class Current: 29/25.35
• CPC Class Codes: G01L 1/148 using semiconductive material, e.g. silicon
• CPC Class Codes: G01L 9/0073 using a semiconductive diaphragm
• CPC Class Codes: Y10T 29/42 Piezoelectric device making
• CPC Class Codes: Y10T 29/49002 Electrical device making

Abstract

A micromachined pressure sensor is formed with a minimum number of masking and processing steps. The structure measures changes in pressure by deflection of structures having capacitive plates external to a sealed cavity so that electrical leads can be readily connected to the plates formed on the structures. The pressure sensor includes a substrate, a base secured to the substrate and a diaphragm secured to the base to define a sealed cavity. A skirt may extend outwardly from the base above the substrate to form one of the plates of the capacitor with another plate formed on the base. Changes in ambient pressure deflect the skirt toward or away from the electrode on the substrate, changing the effective capacitance between the electrodes. Electrical connections may be made to the electrode on the skirt and the electrode on the substrate utilizing electrical connectors which are external to the base and thus external to the sealed cavity.

Claims

1. A method of forming a micromachined pressure sensor comprising:

(a) lithographically masking a semiconductor substrate and etching away the semiconductor substrate forming a relatively thin walled base structure surrounding an open-ended cavity having a single open end;

(b) masking regions of the semiconductor substrate which are not adjacent to, inside, or underneath the base structure forming masked regions of the semiconductor substrate, not masking regions of the semiconductor substrate which are adjacent to, inside, or underneath the base structure forming unmasked regions of the semiconductor substrate;

(c) diffusing a dopant into the base structure and to a selected depth into the unmasked regions of the semiconductor substrate in a region around the base structure which extends outwardly therefrom forming doped portions of the semiconductor substrate in the unmasked regions of the semiconductor substrate and forming undoped portions of the semiconductor substrate in the masked regions of the semiconductor substrate;

(d) bonding the base structure to a structural substrate to form a sealed cavity comprised of the structural substrate, the base structure and the doped portions of the semiconductor substrate; and

(e) etching away the undoped portions of the semiconductor substrate to leave a diaphragm with an outwardly extending skirt that is comprised of the doped portions of the semiconductor substrate and that is integrally attached to the base structure.

2. The method of claim 1 further including before bonding the base structure to the structural substrate the steps of forming an electrode on the structural substrate in positions adjacent to the base structure which will be under the outwardly extending skirt.

3. The method of claim 1 wherein the structural substrate is formed of glass and the step of bonding the base structure to the structural substrate is carried out by anodically bonding.

4. The method of claim 1 wherein the doped portions of the semiconductor substrate are formed in a circular pattern to define a circular skirt which extends outwardly from the base structure.

5. The method of claim 1 wherein the semiconductor substrate is single crystal silicon.

6. The method of claim 5 wherein the dopant is boron.