Capacitor structure and fabrication process

• US 6,460,416 B1
• Filed: 07/10/1998
• Issued: 10/08/2002
• Est. Priority Date: 07/11/1997
• Status: Expired due to Fees

• Current Assignee: Micronas Intermetall GmbH (TDK Corporation)
• Original Assignee: Micronas Intermetall GmbH (TDK Corporation)
• Inventors: Igel, Gunter
• Primary Examiner(s): OEN, WILLIAM L
• Application Number:
  US09/112,849
• Time in Patent Office: 1,551 Days
• Field of Search: 737/18, 737/24, 361/283.4, 361/756
• US Class Current: 73/718
• CPC Class Codes: G01L 9/0073 using a semiconductive diaphragm
• CPC Class Codes: G01L 9/0075 using a ceramic diaphragm, e.g. alumina, fused quartz, glass

Abstract

The invention relates to a capacitor structure with two substrates (1) each having a capacitor electrode (3) deposited on its surface, the substrates (1) being joined together by bump structures located on both sides of the capacitor electrodes (3) such that the capacitor electrodes (3) lie opposite each other and form a capacitor, the distance d between the capacitor electrodes (3) being defined by the height of the bump structures, and measuring connections (5) being provided on one of the substrates (1) for making capacitance measurements.

Claims

1. A capacitor structure comprising two substrates (1) each having a capacitor electrode (3) deposited on a surface, the substrates (1) being joined together by bump structures located on both sides of the capacitor electrodes (3) such that the capacitor electrodes (3) lie opposite each other separated by a distance d and form a capacitor, the distance d between the capacitor electrodes (3) being defined by the structures, and measuring connections (5) being provided on one of the substrates (1) for making capacitance measurements, each of the bump structures including two tapered bumps (4) formed on the substrates, which have been compressed to provide the distance d.

2. The capacitor structure of claim 1, wherein the two bumps (4) of each of the bump structures are soldered together.

3. The capacitor structure of claim 1, wherein the substrates (1) are made of glass.

4. The capacitor structure of claim 1, wherein the substrates (1) are made of a semiconductor material, particularly of silicon.

5. The capacitor structure of claim 1, wherein one of the substrates (1) is designed as a diaphragm, so that the capacitor structure forms a pressure sensor.

6. A capacitor device comprising:

first and second capacitor electrodes; and

,

deformable bump structures formed adjacent to said capacitor electrodes for spacing said first and second capacitor electrodes apart a given distance, each of the bump structures including two tapered bumps (4), which have been compressed to provide the given distance;

wherein said given distance is a function of a desired capacitance of said device.

7. The device of claim 6, further comprising means for enabling measurement of said capacitance of said device when said bump structures are deformed such that the distance between said first and second capacitor electrodes approaches said given distance.

8. The device of claim 6, wherein said distance between said first and second capacitor electrodes is varied to approach said given distance, and further comprising means for enabling measurement of said capacitance of said device between said variances of the distance between said first and second capacitor electrodes.

9. The device of claim 6, wherein said bump structures are aligned such that when engaged said first and second capacitor electrodes are aligned.

10. The device of claim 9 wherein said bump structures are engageable to define said given distance.

11. The device of claim 10, wherein said bump structures are deformable and engageable when heated.

12. The device of claim 10, wherein said bump structures are pressure deformable and engageable.

13. The device of claim 6, wherein said first and second substrates are selected from the group consisting of glass and semiconductor materials.