RF LDMOS on partial SOI substrate

• US 6,461,902 B1
• Filed: 07/18/2000
• Issued: 10/08/2002
• Est. Priority Date: 07/18/2000
• Status: Expired due to Fees

• Current Assignee: Institute of Microelectronics
• Original Assignee: Institute of Microelectronics
• Inventors: Feng, Hanhua, Xu, Shuming, Foo, Pang-Dow
• Primary Examiner(s): Fourson, George
• Assistant Examiner(s): MANDALA, MICHELLE
• Application Number:
  US09/618,263
• Time in Patent Office: 812 Days
• Field of Search: 438/163, 438/286, 438/296, 438/307, 438/923, 438/FOR.188
• US Class Current: 438/163
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/4175 for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: Y10S 438/923 Diffusion through a layer

Abstract

In the prior art LDMOSFET devices capable of handling high power have been made by locating the source contact on the bottom surface of the device, allowing for good heat sinking, with connection to the source region being made through a sinker. However, this structure has poor high frequency characteristics. Also in the prior art, good high frequency performance has been achieved by introducing a dielectric layer immediately below the source/drain regions (SOI) but this structure has poor handling capabilities. The present invention achieves both good high frequency behavior as well as good power capability in the same device. Instead of inserting a dielectric layer over the entire cross-section of the device, the dielectric layer is limited to being below the heavily doped section of the drain with a small amount of overlap into the lightly doped section. The structure is described in detail together with a process for manufacturing it.

Claims

1. A process for manufacturing a field effect transistor, comprising:

providing a body of P+ silicon having left and right edges;

epitaxially depositing a layer of P−

silicon, having a first upper surface, on the P+ silicon body;

forming a dielectric layer having a second upper surface that runs parallel to said first upper surface contiguous to the right edge and that extends away from the right edge by a first amount, said second upper surface being at a depth below said first upper surface;

then forming a sinker of P+ silicon contiguous to the left edge that extends away from the left edge by a second amount and downwards from said first upper surface into the P+ body;

forming a layer of N−

silicon, having a thickness less than said depth, that extends away from the right edge by a third amount;

through a mask, forming first and second areas of a layer of N+ silicon that has a thickness equal to said depth, the first area extending away from the right edge for a first width that is less than said third amount and the second area being adjacent to, and extending away from, the sinker for a second width whereby a gap is left between the first and second N+ areas;

forming a layer of gate oxide over said gap and depositing a gate electrode over the gate oxide;

forming a layer of a conductive material on said first upper surface that contacts both the P+ sinker and the source region; and

forming a drain electrode over the second N+ drain region.

2. The process of claim 1 wherein the step of forming the dielectric layer further comprises:

forming a layer of oxide on said first upper surface and then patterning and etching said oxide layer to form a mask that defines a trench running parallel to said right edge;

forming the trench by etching silicon unprotected by the mask down to said depth;

selectively depositing a layer of silicon nitride on all vertical sidewalls of said trench;

oxidizing all exposed silicon to a depth of between about 0.45 and 0.55 microns;

removing all silicon nitride;

depositing polysilicon until the trench has been overfilled; and

etching back the polysilicon until the oxide mask has been removed and the polysilicon has an upper surface that is coplanar with said first upper surface.

3. The process of claim 2 wherein the step of oxidizing all exposed silicon further comprises furnance heating for between about 65 and 75 minutes at a temperature between about 1,049 and 1,051°

C.

4. The process of claim 1 wherein said second amount that the sinker of P+ silicon extends away from the left edge is between about 4 and 10 microns.

5. The process of claim 1 wherein the depth below said first upper surface of the second upper surface is between about 8,000 and 9,000 Angstroms.

6. The process of claim 1 wherein said first amount that the dielectric layer extends away from the right edge is between about 11 and 12 microns.

7. The process of claim 1 wherein said third amount that the N−

layer extends away from the right edge is between about 2 and 4.5 microns.