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RF LDMOS on partial SOI substrate

  • US 6,461,902 B1
  • Filed: 07/18/2000
  • Issued: 10/08/2002
  • Est. Priority Date: 07/18/2000
  • Status: Expired due to Fees
First Claim
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1. A process for manufacturing a field effect transistor, comprising:

  • providing a body of P+ silicon having left and right edges;

    epitaxially depositing a layer of P−

    silicon, having a first upper surface, on the P+ silicon body;

    forming a dielectric layer having a second upper surface that runs parallel to said first upper surface contiguous to the right edge and that extends away from the right edge by a first amount, said second upper surface being at a depth below said first upper surface;

    then forming a sinker of P+ silicon contiguous to the left edge that extends away from the left edge by a second amount and downwards from said first upper surface into the P+ body;

    forming a layer of N−

    silicon, having a thickness less than said depth, that extends away from the right edge by a third amount;

    through a mask, forming first and second areas of a layer of N+ silicon that has a thickness equal to said depth, the first area extending away from the right edge for a first width that is less than said third amount and the second area being adjacent to, and extending away from, the sinker for a second width whereby a gap is left between the first and second N+ areas;

    forming a layer of gate oxide over said gap and depositing a gate electrode over the gate oxide;

    forming a layer of a conductive material on said first upper surface that contacts both the P+ sinker and the source region; and

    forming a drain electrode over the second N+ drain region.

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