Power MOS device with improved gate charge performance

• US 6,461,918 B1
• Filed: 12/20/1999
• Issued: 10/08/2002
• Est. Priority Date: 12/20/1999
• Status: Expired due to Term

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Calafut, Daniel S.
• Primary Examiner(s): Jackson, Jerome
• Assistant Examiner(s): Rao, Shrinivas H.
• Application Number:
  US09/468,269
• Time in Patent Office: 1,023 Days
• Field of Search: 438/259, 438/270, 438/271, 438/587, 438/588, 438/589, 438/315, 438/593
• US Class Current: 438/270
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4916 the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/4983 with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A double-diffused metal-oxide-semiconductor (“DMOS”) field-effect transistor with an improved gate structure. The gate structure includes a first portion of a first conductivity type for creating electron flow from the source to the drain when a charge is applied to the gate. The gate structure includes a second portion of a second conductivity type having a polarity that is opposite a polarity of the first conductivity type, for decreasing a capacitance charge under the gate. A second structure for decreasing a capacitance under the gate includes an implant region in the semiconductor substrate between a channel region, where the implant region is doped to have a conductivity opposite the channel region.

Claims

1. A method of fabricating a double-diffused metal oxide semiconductor (DMOS) device, the method comprising:

forming a body region of a first conductivity type in a semiconductor substrate having a drain region of a second conductivity type;

forming a source region of the second conductivity type in the body region;

forming a trench in the semiconductor substrate;

lining the trench with a dielectric layer;

forming a first polysilicon gate portion to an intermediate depth of the trench;

implanting a dopant of the first conductivity type into the first polysilicon gate portion;

forming a second polysilicon gate portion in the trench over the first polysilicon gate portion to a level substantially equal to a top surface of the silicon substrate;

implanting a dopant of the second conductivity type into the second polysilicon gate portion;

etching away an intermediate portion of the second polysilicon gate portion down to the first polysilicon gate portion; and

forming a polycide strap layer over the first polysilicon gate portion in the intermediate portion and on opposite side walls of the second polysilicon gate portion.

2. The method of claim 1, further comprising depositing a conductive material in the intermediate portion to the level substantially equal to the top surface of the silicon substrate.

3. The method of claim 1, wherein the first conductivity type is p-type and the second conductivity type is n-type.

4. The method of claim 1, further comprising, after forming the polycide strap layer:

forming an insulator over the polycide strap layer, in the trench and over the top of the trench.

5. The method of claim 4 wherein the insulator extends over the source region.

6. The method of claim 4 further comprising:

forming a metal layer over the insulator.

7. The method of claim 1 wherein forming the source region occurs after forming the trench.

8. The method of claim 1 further comprising, after forming the polycide strap layer:

forming an insulator over the polycide strap layer, in the trench and over the top of the trench, wherein the insulator comprises borophosphosilicon glass (BPSG).

9. The method of claim 1 wherein implanting a dopant of the first conductivity type into the first polysilicon gate portion comprises:

doping the first polysilicon gate portion with a sufficient amount of dopant to minimize the capacitance in an accumulation area for a predetermined voltage.

10. The method of claim 1 further comprising, after forming the polycide strap layer:

forming an insulator over the polycide strap layer, in the trench and over the top of the trench; and

forming a metal layer over the insulator to provide electrical contact to the source region.

11. The method of claim 1 wherein the DMOS device is a power MOS device.