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Power MOS device with improved gate charge performance

  • US 6,461,918 B1
  • Filed: 12/20/1999
  • Issued: 10/08/2002
  • Est. Priority Date: 12/20/1999
  • Status: Expired due to Term
First Claim
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1. A method of fabricating a double-diffused metal oxide semiconductor (DMOS) device, the method comprising:

  • forming a body region of a first conductivity type in a semiconductor substrate having a drain region of a second conductivity type;

    forming a source region of the second conductivity type in the body region;

    forming a trench in the semiconductor substrate;

    lining the trench with a dielectric layer;

    forming a first polysilicon gate portion to an intermediate depth of the trench;

    implanting a dopant of the first conductivity type into the first polysilicon gate portion;

    forming a second polysilicon gate portion in the trench over the first polysilicon gate portion to a level substantially equal to a top surface of the silicon substrate;

    implanting a dopant of the second conductivity type into the second polysilicon gate portion;

    etching away an intermediate portion of the second polysilicon gate portion down to the first polysilicon gate portion; and

    forming a polycide strap layer over the first polysilicon gate portion in the intermediate portion and on opposite side walls of the second polysilicon gate portion.

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