Power MOS device with improved gate charge performance
First Claim
1. A method of fabricating a double-diffused metal oxide semiconductor (DMOS) device, the method comprising:
- forming a body region of a first conductivity type in a semiconductor substrate having a drain region of a second conductivity type;
forming a source region of the second conductivity type in the body region;
forming a trench in the semiconductor substrate;
lining the trench with a dielectric layer;
forming a first polysilicon gate portion to an intermediate depth of the trench;
implanting a dopant of the first conductivity type into the first polysilicon gate portion;
forming a second polysilicon gate portion in the trench over the first polysilicon gate portion to a level substantially equal to a top surface of the silicon substrate;
implanting a dopant of the second conductivity type into the second polysilicon gate portion;
etching away an intermediate portion of the second polysilicon gate portion down to the first polysilicon gate portion; and
forming a polycide strap layer over the first polysilicon gate portion in the intermediate portion and on opposite side walls of the second polysilicon gate portion.
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Accused Products
Abstract
A double-diffused metal-oxide-semiconductor (“DMOS”) field-effect transistor with an improved gate structure. The gate structure includes a first portion of a first conductivity type for creating electron flow from the source to the drain when a charge is applied to the gate. The gate structure includes a second portion of a second conductivity type having a polarity that is opposite a polarity of the first conductivity type, for decreasing a capacitance charge under the gate. A second structure for decreasing a capacitance under the gate includes an implant region in the semiconductor substrate between a channel region, where the implant region is doped to have a conductivity opposite the channel region.
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Citations
11 Claims
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1. A method of fabricating a double-diffused metal oxide semiconductor (DMOS) device, the method comprising:
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forming a body region of a first conductivity type in a semiconductor substrate having a drain region of a second conductivity type;
forming a source region of the second conductivity type in the body region;
forming a trench in the semiconductor substrate;
lining the trench with a dielectric layer;
forming a first polysilicon gate portion to an intermediate depth of the trench;
implanting a dopant of the first conductivity type into the first polysilicon gate portion;
forming a second polysilicon gate portion in the trench over the first polysilicon gate portion to a level substantially equal to a top surface of the silicon substrate;
implanting a dopant of the second conductivity type into the second polysilicon gate portion;
etching away an intermediate portion of the second polysilicon gate portion down to the first polysilicon gate portion; and
forming a polycide strap layer over the first polysilicon gate portion in the intermediate portion and on opposite side walls of the second polysilicon gate portion. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
forming an insulator over the polycide strap layer, in the trench and over the top of the trench.
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5. The method of claim 4 wherein the insulator extends over the source region.
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6. The method of claim 4 further comprising:
forming a metal layer over the insulator.
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7. The method of claim 1 wherein forming the source region occurs after forming the trench.
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8. The method of claim 1 further comprising, after forming the polycide strap layer:
forming an insulator over the polycide strap layer, in the trench and over the top of the trench, wherein the insulator comprises borophosphosilicon glass (BPSG).
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9. The method of claim 1 wherein implanting a dopant of the first conductivity type into the first polysilicon gate portion comprises:
doping the first polysilicon gate portion with a sufficient amount of dopant to minimize the capacitance in an accumulation area for a predetermined voltage.
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10. The method of claim 1 further comprising, after forming the polycide strap layer:
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forming an insulator over the polycide strap layer, in the trench and over the top of the trench; and
forming a metal layer over the insulator to provide electrical contact to the source region.
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11. The method of claim 1 wherein the DMOS device is a power MOS device.
Specification