GENERATING A TAIL CURRENT FOR A DIFFERENTIAL TRANSISTOR PAIR USING A CAPACITIVE DEVICE TO PROJECT A CURRENT FLOWING THROUGH A CURRENT SOURCE DEVICE ONTO A NODE HAVING A DIFFERENT VOLTAGE THAN THE CURRENT SOURCE DEVICE

• US 6,462,584 B1
• Filed: 02/11/2000
• Issued: 10/08/2002
• Est. Priority Date: 02/13/1999
• Status: Expired due to Term

• Current Assignee: InnoMemory, LLC (Jeffrey M. Gross)
• Original Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Inventors: Proebsting, Robert J.
• Primary Examiner(s): Lam, Tuan T.
• Assistant Examiner(s): Nguyen, Hiep
• Application Number:
  US09/503,108
• Time in Patent Office: 970 Days
• Field of Search: 330/258, 330/261, 330/273, 330/285, 330/297, 330/253, 327/55, 327/53, 327/56, 327/57, 327/52, 365/203, 365/204
• US Class Current: 327/52
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 2207/104 Embedded memory devices, e.g. memories with a processing device on the same die or ASIC memory designs
• CPC Class Codes: G11C 2207/229 Timing of a write operation sense amplifier timing G11C7/06, G11C7/08
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: H10B 12/488 Word lines
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures

Abstract

A current tail circuit and method for a differential transistor pair affords the capability of sensing an input differential signal having a low common mode voltage when using, for example, an NMOS differential transistor pair. A current source device and a capacitor may be employed to provide at the common node of the differential transistor pair what appears to be a constant current source connected to a “negative voltage.” In one embodiment particularly useful when using an NMOS differential pair, one terminal of a capacitor is precharged to VDD and the other terminal is precharged to VSS (i.e., ground). When the amplifier needs to sense its differential input signal, a control signal turns off precharge transistors and couples the capacitor terminal previously precharged to VSS to the common-source node of a differential transistor pair. The capacitor terminal previously precharged to VDD is driven toward VSS, preferably with a controlled current source, which couples the common-source node of the differential pair from VSS toward a voltage below VSS. As soon as the common-source node voltage is low enough for at least one side of the differential pair to conduct a current substantially equal to the controlled current source, the common-source node voltage is substantially clamped at that voltage. The actual voltage resulting on the common-source node depends on the transistor characteristics, the particular voltages present on the gates of the differential pair, and the magnitude of the controlled current source. For some operating conditions, this voltage may be above ground rather than below ground, but the “tail” current of the differential pair nonetheless remains equal to the magnitude of current through the device driving the other terminal of the capacitor from VDD toward VSS.

Claims

1. In an integrated circuit including a differential transistor pair having a common node connecting a respective first current handling terminal of each transistor within the pair, a method of providing a tail current for the differential transistor pair comprising:

precharging a capacitive device having a first terminal and a second terminal;

providing a current path from the common node of the differential transistor pair to the first terminal of the capacitive device; and

driving, with a substantially constant first current, the voltage of the second terminal of the precharged capacitive device in a direction to capacitively couple the first terminal and, by way of the current path, the common node to respective voltages sufficient in magnitude and polarity to cause a current, substantially equal to the first current, to flow collectively through one or both transistors of the differential transistor pair;

wherein the first current flows as a displacement current through the capacitive device and is projected onto the common node, thereby providing a dynamic tail current for the differential transistor pair substantially equal in magnitude to the first current.

2. A method as in claim 1 wherein:

the voltage of the second terminal of the capacitive device, while the first current flows through the capacitive device as a displacement current, changes at a rate that substantially exceeds the rate of voltage change of the first terminal of the capacitive device.

3. A method as in claim 1 wherein:

each transistor of the differential transistor pair comprises a field effect transistor; and

the common node comprises a common-source node.

4. A method as in claim 1 wherein:

each transistor of the differential transistor pair comprises a bipolar junction transistor; and

the common node comprises a common-emitter node.

5. A method as in claim 1 wherein:

while the first current flows through the capacitive device as a displacement current, the first terminal of the capacitive device assumes a voltage at which the current collectively flowing through one or both transistors of the differential transistor pair remains substantially equal to the first current.

6. A method as in claim 5 wherein:

for certain values of input voltages applied to the differential transistor pair, certain transistor characteristics of the differential transistor pair, and certain magnitudes of the first current, the voltage assumed by the first terminal of the capacitive device is outside a range of voltages bounded by the highest power supply voltage and the lowest power supply voltage operably received by the integrated circuit.

7. A method as in claim 5 wherein:

for certain values of input voltages applied to the differential transistor pair, certain transistor characteristics of the differential transistor pair, and certain magnitudes of the first current, the voltage assumed by the first terminal of the capacitive device is within a range of voltages bounded by the highest power supply voltage and the lowest power supply voltage operably received by the integrated circuit.

8. A method as in claim 1 wherein:

the capacitive device is disposed in close local proximity to, and uniquely associated with, the differential transistor pair.

9. A method as in claim 1 wherein:

the capacitive device is disposed in close local proximity to, and also uniquely associated with, said differential transistor pair and another differential transistor pair; and

each differential transistor pair includes a respective gating circuit connecting the respective common node thereof to the first terminal of the capacitive device.

11. A method as in claim 1 wherein:

the current path includes at least one transistor connecting the common node to the first terminal of the capacitive device, which at least one transistor is enabled to conduct current therebetween at least while driving the second terminal of the capacitive device.

12. A method as in claim 11 wherein:

while driving the second terminal of the capacitive device, the current path includes no device configured to function as a constant current source; and

the magnitude of the displacement current is controlled by a circuit driving the second terminal of the capacitive device with the first current.

13. A method as in claim 11 wherein:

while driving the second terminal of the capacitive device, the current path includes at least one device configured to function as a constant current source; and

the magnitude of the displacement current is controlled by the constant current source.

14. A method as in claim 1 further comprising:

developing a differential output signal at respective second current handling terminals of the differential transistor pair while the displacement current through the capacitive device provides a tail current for the differential transistor pair; and

utilizing the differential output signal in a subsequent circuit coupled to the differential transistor pair.

15. A method as in claim 14 wherein the differential transistor pair is incorporated within a linear amplifier circuit.

16. A method as in claim 15 wherein the integrated circuit further comprises:

a pair of load devices, each respectively coupled between the respective second current handling terminal of each transistor within the differential transistor pair and a power supply terminal.

28. A method as in claim 1 wherein:

the capacitive device comprises a field effect transistor connected to function as a capacitor.

29. A method as in claim 1 wherein:

the capacitive device comprises a capacitor.

30. A method as in claim 1 wherein:

the capacitive device comprises a semiconductor junction reversed biased to function as a capacitor.

31. A method as in claim 1 wherein the driving step comprises:

driving the second terminal of the capacitive device toward a power supply voltage.

32. A method as in claim 31 wherein the driving step further comprises:

driving the second terminal of the capacitive device through a switch transistor in series with a current source device.

33. A method as in claim 32 wherein the current source device comprises:

a transistor biased with a reference voltage coupled to the control terminal thereof.

34. A method as in claim 1 wherein:

each transistor of the differential transistor pair comprises a field effect transistor and the common node comprises a common-source node;

while the first current flows through the capacitive device as a displacement current, the first terminal of the capacitive device assumes a voltage at which the current collectively flowing through one or both transistors of the differential transistor pair remains substantially equal to the first current; and

for certain values of input voltages applied to the differential transistor pair, certain transistor characteristics of the differential transistor pair, and certain magnitudes of the first current, the voltage assumed by the first terminal of the capacitive device is outside a range of voltages bounded by the highest power supply voltage and the lowest power supply voltage operably received by the integrated circuit.

35. A method as in claim 34 wherein:

the capacitive device comprises a field effect transistor connected to function as a capacitor and disposed in close local proximity to, and uniquely associated with, the differential transistor pair; and

the current path includes at least one transistor connecting the common node to the first terminal of the capacitive device, which at least one transistor is enabled to conduct current therebetween at least while driving the second terminal of the capacitive device.

37. A method as in claim 35 further comprising:

coupling an external input signal to a control terminal of one transistor of the differential transistor pair; and

coupling a complementary external input signal to a control terminal of the other transistor of the differential transistor pair.

38. A method as in claim 34 wherein the driving step further comprises:

driving the second terminal of the capacitive device through a switch transistor in series with a current source device.

10. In an integrated circuit including a differential transistor pair having a common node connecting a respective first current handling terminal of each transistor within the pair, a method of providing a tail current for the differential transistor pair comprising:

precharging a capacitive device having a first terminal and a second terminal;

providing a current path from the common node of the differential transistor pair to the first terminal of the capacitive device; and

driving, with a first current, the voltage of the second terminal of the precharged capacitive device in a direction to capacitively couple the first terminal and, by way of the current path, the common node to respective voltages sufficient in magnitude and polarity to cause a current, substantially equal to the first current, to flow collectively through one or both transistors of the differential transistor pair;

wherein the first current flows as a displacement current through the capacitive device and is projected onto the common node, thereby providing a dynamic tail current for the differential transistor pair substantially equal in magnitude to the first current; and

wherein the current path consists of a direct wired connection between the common node and the first terminal of the capacitive device.

17. In an integrated circuit including a differential transistor pair having a common node connecting a respective first current handling terminal of each transistor within the pair, a method of providing a tail current for the differential transistor pair comprising:

precharging a capacitive device having a first terminal and a second terminal;

providing a current path from the common node of the differential transistor pair to the first terminal of the capacitive device; and

driving, with a controlled first current, the voltage of the second terminal of the precharged capacitive device in a direction to capacitively couple the first terminal and, by way of the current path, the common node to respective voltages sufficient in magnitude and polarity to cause a current, substantially equal to the first current, to flow collectively through one or both transistors of the differential transistor pair;

wherein the first current flows as a displacement current through the capacitive device and is projected onto the common node, thereby providing a dynamic tail current for the differential transistor pair substantially equal in magnitude to the first current;

developing a differential output signal at respective second current handling terminals of the differential transistor pair while the displacement current through the capacitive device provides a tail current for the differential transistor pair; and

utilizing the differential output signal in a subsequent circuit coupled to the differential transistor pair; and

wherein the differential transistor pair is incorporated within a latching amplifier circuit having a separate latch enable input.

18. In an integrated circuit including a differential transistor pair having a common node connecting a respective first current handling terminal of each transistor within the pair, a method of providing a tail current for the differential transistor pair comprising:

precharging a capacitive device having a first terminal and a second terminal;

providing a current path from the common node of the differential transistor pair to the first terminal of the capacitive device; and

driving, with a controlled first current, the voltage of the second terminal of the precharged capacitive device in a direction to capacitively couple the first terminal and, by way of the current path, the common node to respective voltages sufficient in magnitude and polarity to cause a current, substantially equal to the first current, to flow collectively through one or both transistors of the differential transistor pair;

wherein the first current flows as a displacement current through the capacitive device and is projected onto the common node, thereby providing a dynamic tail current for the differential transistor pair substantially equal in magnitude to the first current;

developing a differential output signal at respective second current handling terminals of the differential transistor pair while the displacement current through the capacitive device provides a tail current for the differential transistor pair; and

utilizing the differential output signal in a subsequent circuit coupled to the differential transistor pair;

wherein the differential transistor pair is incorporated within a latching amplifier circuit having no separate latch enable input; and

wherein the latching amplifier circuit latches as a result of the differential output signal developed by the differential transistor pair.

19. A method as in claim 18 wherein the integrated circuit further comprises:

a pair of cross-coupled inverters configured as a latch, each inverter'"'"'s output respectively connected to the other inverter'"'"'s input and also connected to a respective second current handling terminal of the transistors within the differential transistor pair;

wherein the displacement current flowing through the capacitive device and providing a tail current for the differential transistor pair provides a strobe signal for the latch.

20. In an integrated circuit including a differential transistor pair having a common node connecting a respective first current handling terminal of each transistor within the pair, a method of providing a tail current for the differential transistor pair comprising:

precharging a capacitive device having a first terminal and a second terminal;

providing a current path from the common node of the differential transistor pair to the first terminal of the capacitive device; and

driving, with a controlled first current, the voltage of the second terminal of the precharged capacitive device in a direction to capacitively couple the first terminal and, by way of the current path, the common node to respective voltages sufficient in magnitude and polarity to cause a current, substantially equal to the first current, to flow collectively through one or both transistors of the differential transistor pair;

wherein the first current flows as a displacement current through the capacitive device and is projected onto the common node, thereby providing a dynamic tail current for the differential transistor pair substantially equal in magnitude to the first current;

developing a differential output signal at respective second current handling terminals of the differential transistor pair while the displacement current through the capacitive device provides a tail current for the differential transistor pair; and

utilizing the differential output signal in a subsequent circuit coupled to the differential transistor pair; and

wherein the differential transistor pair is incorporated within an external input buffer of the integrated circuit.

21. A method as in claim 20 wherein:

the integrated circuit includes a memory array.

22. A method as in claim 20 wherein:

the driving step is controlled to occur at a time relative to an external clock signal received by the integrated circuit.

23. A method as in claim 22 wherein:

the external input buffers of the integrated circuit are strobed at a time relative to an external clock signal received by the integrated circuit.

24. A method as in claim 20 further comprising:

coupling an external input signal to a control terminal of one transistor of the differential transistor pair; and

coupling a reference voltage to a control terminal of the other transistor of the differential transistor pair.

25. A method as in claim 20 further comprising:

coupling an external input signal to a control terminal of one transistor of the differential transistor pair; and

coupling a complementary external input signal to a control terminal of the other transistor of the differential transistor pair.

26. In an integrated circuit including a differential transistor pair having a common node connecting a respective first current handling terminal of each transistor within the pair, a method of providing a tail current for the differential transistor pair comprising:

precharging a capacitive device having a first terminal and a second terminal;

providing a current path from the common node of the differential transistor pair to the first terminal of the capacitive device; and

driving, with a controlled first current, the voltage of the second terminal of the precharged capacitive device in a direction to capacitively couple the first terminal and, by way of the current path, the common node to respective voltages sufficient in magnitude and polarity to cause a current, substantially equal to the first current, to flow collectively through one or both transistors of the differential transistor pair;

wherein the first current flows as a displacement current through the capacitive device and is projected onto the common node, thereby providing a dynamic tail current for the differential transistor pair substantially equal in magnitude to the first current;

developing a differential output signal at respective second current handling terminals of the differential transistor pair while the displacement current through the capacitive device provides a tail current for the differential transistor pair; and

utilizing the differential output signal in a subsequent circuit coupled to the differential transistor pair; and

wherein the differential transistor pair is incorporated within an I/O bus line amplifier of a memory array within the integrated circuit.

27. In an integrated circuit including a differential transistor pair having a common node connecting a respective first current handling terminal of each transistor within the pair, a method of providing a tail current for the differential transistor pair comprising:

precharging a capacitive device having a first terminal and a second terminal;

providing a current path from the common node of the differential transistor pair to the first terminal of the capacitive device; and

driving, with a controlled first current, the voltage of the second terminal of the precharged capacitive device in a direction to capacitively couple the first terminal and, by way of the current path, the common node to respective voltages sufficient in magnitude and polarity to cause a current, substantially equal to the first current, to flow collectively through one or both transistors of the differential transistor pair;

wherein the first current flows as a displacement current through the capacitive device and is projected onto the common node, thereby providing a dynamic tail current for the differential transistor pair substantially equal in magnitude to the first current;

developing a differential output signal at respective second current handling terminals of the differential transistor pair while the displacement current through the capacitive device provides a tail current for the differential transistor pair; and

utilizing the differential output signal in a subsequent circuit coupled to the differential transistor pair; and

wherein the differential transistor pair is incorporated within a bit line read amplifier of a memory array within the integrated circuit.

36. In an integrated circuit including a differential transistor pair having a common node connecting a respective first current handling terminal of each transistor within the pair, a method of providing a tail current for the differential transistor pair comprising:

precharging a capacitive device having a first terminal and a second terminal;

providing a current path from the common node of the differential transistor pair to the first terminal of the capacitive device; and

driving, with a controlled first current, the voltage of the second terminal of the precharged capacitive device in a direction to capacitively couple the first terminal and, by way of the current path, the common node to respective voltages sufficient in magnitude and polarity to cause a current, substantially equal to the first current, to flow collectively through one or both transistors of the differential transistor pair;

wherein the first current flows as a displacement current through the capacitive device and is projected onto the common node, thereby providing a dynamic tail current for the differential transistor pair substantially equal in magnitude to the first current;

wherein each transistor of the differential transistor pair comprises a field effect transistor and the common node comprises a common-source node;

wherein while the first current flows through the capacitive device as a displacement current, the first terminal of the capacitive device assumes a voltage at which the current collectively flowing through one or both transistors of the differential transistor pair remains substantially equal to the first current; and

wherein for certain values of input voltages applied to the differential transistor pair, certain transistor characteristics of the differential transistor pair, and certain magnitudes of the first current, the voltage assumed by the first terminal of the capacitive device is outside a range of voltages bounded by the highest power supply voltage and the lowest power supply voltage operably received by the integrated circuit;

wherein the capacitive device comprises a field effect transistor connected to function as a capacitor and disposed in close local proximity to, and uniquely associated with, the differential transistor pair;

wherein the current path includes at least one transistor connecting the common node to the first terminal of the capacitive device, which at least one transistor is enabled to conduct current therebetween at least while driving the second terminal of the capacitive device;

said method further comprising;

coupling an external input signal to a control terminal of one transistor of the differential transistor pair; and

coupling a reference voltage to a control terminal of the other transistor of the differential transistor pair.

39. An integrated circuit comprising:

a first transistor and a second transistor configured as a differential transistor pair having a common node connecting respective first current handling terminals of each transistor within the pair;

capacitive means having a first terminal and a second terminal;

means for precharging the capacitive means to a voltage thereacross;

means for providing a current path from the common node of the differential transistor pair to the first terminal of the capacitive means; and

means for driving, with a substantially constant first current, the voltage of the second terminal of the precharged capacitive means in a direction to capacitively couple the first terminal and, by way of the current path, the common node to respective voltages sufficient in magnitude and polarity to cause a current, substantially equal to the first current, to flow collectively through one or both transistors of the differential transistor pair;

wherein the first current flows as a displacement current through the capacitive means and is projected onto the common node, thereby providing a dynamic tail current for the differential transistor pair substantially equal in magnitude to the first current.

40. An integrated circuit as in claim 39 wherein:

the voltage of the second terminal of the capacitive means, while the first current flows through the capacitive means as a displacement current, changes at a rate that substantially exceeds the rate of voltage change of the first terminal of the capacitive means.

41. An integrated circuit as in claim 39 wherein:

the capacitive means is disposed in close proximity to, and uniquely associated with, the differential transistor pair.

42. An integrated circuit as in claim 39 wherein:

the capacitive means comprises a field effect transistor connected to function as a capacitor.

43. An integrated circuit as in claim 39 wherein:

the capacitive means comprises a capacitor.

44. An integrated circuit as in claim 39 wherein:

the driving means comprises a switch transistor in series with a current source device, together coupled between the second terminal of the capacitive means and a power supply terminal.

46. An integrated circuit as in claim 39 wherein:

the current path providing means comprises at least one transistor coupled between the common node and the first terminal of the capacitive means, which transistor is conductive at least during a time when the driving means is enabled to drive the second terminal of the capacitive means.

47. An integrated circuit as in claim 46 wherein:

the at least one transistor coupled between the common node and the first terminal of the capacitive means is responsive to an enable signal which is active when the driving means is enabled.

45. An integrated circuit comprising:

a first transistor and a second transistor configured as a differential transistor pair having a common node connecting respective first current handling terminals of each transistor within the pair;

capacitive means having a first terminal and a second terminal;

means for precharging the capacitive means to a voltage thereacross;

means for providing a current path from the common node of the differential transistor pair to the first terminal of the capacitive means; and

means for driving, with a first current, the voltage of the second terminal of the precharged capacitive means in a direction to capacitively couple the first terminal and, by way of the current path, the common node to respective voltages sufficient in magnitude and polarity to cause a current, substantially equal to the first current, to flow collectively through one or both transistors of the differential transistor pair;

wherein the first current flows as a displacement current through the capacitive means and is projected onto the common node, thereby providing a dynamic tail current for the differential transistor pair substantially equal in magnitude to the first current; and

wherein the current path providing means comprises a direct wired connection between the common node and the first terminal of the capacitive means.

48. An integrated circuit comprising:

a first transistor and a second transistor configured as a differential transistor pair having a common node connecting respective first current handling terminals of each transistor within the pair;

a capacitive device having a first terminal and a second terminal;

a precharge circuit for precharging, during a first time period, the capacitive device to an initial voltage thereacross, said first terminal of the capacitive device being coupled to a source of a first voltage and said second terminal of the capacitive device being coupled to a source of a second voltage;

a current path from the common node of the differential transistor pair to the first terminal of the capacitive device; and

a driver circuit responsive to a first control signal, for driving, with a substantially constant first current during a second time period, the voltage of the second terminal of the capacitive device in a direction to capacitively couple the first terminal and, by way of the current path, the common node to respective voltages sufficient in magnitude and polarity to cause a current, substantially equal in magnitude to the first current, to flow collectively through one or both transistors of the differential transistor pair;

wherein the first current flows as a displacement current through the capacitive device and is projected onto the common node, thereby providing a dynamic tail current for the differential transistor pair substantially equal in magnitude to the first current.

49. An integrated circuit as in claim 48 wherein:

the voltage of the second terminal of the capacitive device, while the first current flows through the capacitive device as a displacement current, changes at a rate that substantially exceeds the rate of voltage change of the first terminal of the capacitive device.

50. An integrated circuit as in claim 48 wherein:

each transistor of the differential transistor pair comprises a field effect transistor; and

the common node comprises a common-source node.

51. An integrated circuit as in claim 48 wherein:

each transistor of the differential transistor pair comprises a bipolar junction transistor; and

the common node comprises a common-emitter node.

52. An integrated circuit as in claim 48 wherein:

each transistor of the differential transistor pair comprises a gallium arsenide MESFET transistor; and

the common node comprises a common-source node.

53. An integrated circuit as in claim 48 wherein:

while the first current flows through the capacitive device as a displacement current, the first terminal of the capacitive device assumes a voltage at which the current collectively flowing through one or both transistors of the differential transistor pair remains substantially equal to the first current.

56. An integrated circuit as in claim 48 wherein:

the capacitive device is disposed in close local proximity to, and uniquely associated with, the differential transistor pair.

73. An integrated circuit as in claim 48 wherein:

the capacitive device comprises a field effect transistor connected to function as a capacitor.

74. An integrated circuit as in claim 48 wherein:

the capacitive device comprises a capacitor.

75. An integrated circuit as in claim 48 wherein:

the driver circuit is arranged to drive the second terminal of the capacitive device toward a power supply voltage.

79. An integrated circuit as in claim 48 wherein:

each transistor of the differential transistor pair comprises a field effect transistor and the common node comprises a common-source node; and

while the first current flows through the capacitive device as a displacement current, the first terminal of the capacitive device assumes a voltage at which the current collectively flowing through one or both transistors of the differential transistor pair remains substantially equal to the first current.

54. An integrated circuit comprising:

a first transistor and a second transistor configured as a differential transistor pair having a common node connecting respective first current handling terminals of each transistor within the pair;

a capacitive device having a first terminal and a second terminal;

a precharge circuit for precharging, during a first time period, the capacitive device to an initial voltage thereacross, said first terminal of the capacitive device being coupled to a source of a first voltage and said second terminal of the capacitive device being coupled to a source of a second voltage;

a current path from the common node of the differential transistor pair to the first terminal of the capacitive device; and

a driver circuit responsive to a first control signal, for driving, with a first current during a second time period, the voltage of the second terminal of the capacitive device in a direction to capacitively couple the first terminal and, by way of the current path, the common node to respective voltages sufficient in magnitude and polarity to cause a current, substantially equal in magnitude to the first current, to flow collectively through one or both transistors of the differential transistor pair;

wherein the first current flows as a displacement current through the capacitive device and is projected onto the common node, thereby providing a dynamic tail current for the differential transistor pair substantially equal in magnitude to the first current;

wherein while the first current flows through the capacitive device as a displacement current, the first terminal of the capacitive device assumes a voltage at which the current collectively flowing through one or both transistors of the differential transistor pair remains substantially equal to the first current; and

wherein the driver circuit is arranged to drive the second terminal of the capacitive device from a voltage substantially equal to a first power supply voltage operably received by the integrated circuit toward a voltage substantially equal to a second power supply voltage operably received by the integrated circuit.

55. An integrated circuit comprising:

a first transistor and a second transistor configured as a differential transistor pair having a common node connecting respective first current handling terminals of each transistor within the pair;

a capacitive device having a first terminal and a second terminal;

a precharge circuit for precharging, during a first time period, the capacitive device to an initial voltage thereacross, said first terminal of the capacitive device being coupled to a source of a first voltage and said second terminal of the capacitive device being coupled to a source of a second voltage;

a current path from the common node of the differential transistor pair to the first terminal of the capacitive device; and

a driver circuit responsive to a first control signal, for driving, with a first current during a second time period, the voltage of the second terminal of the capacitive device in a direction to capacitively couple the first terminal and, by way of the current path, the common node to respective voltages sufficient in magnitude and polarity to cause a current, substantially equal in magnitude to the first current, to flow collectively through one or both transistors of the differential transistor pair;

wherein the first current flows as a displacement current through the capacitive device and is projected onto the common node, thereby providing a dynamic tail current for the differential transistor pair substantially equal in magnitude to the first current;

wherein while the first current flows through the capacitive device as a displacement current, the first terminal of the capacitive device assumes a voltage at which the current collectively flowing through one or both transistors of the differential transistor pair remains substantially equal to the first current; and

wherein the magnitude of the displacement current through the capacitive device is largely controlled by the output impedance of the driver circuit.

57. An integrated circuit comprising:

a first transistor and a second transistor configured as a differential transistor pair having a common node connecting respective first current handling terminals of each transistor within the pair;

a capacitive device having a first terminal and a second terminal;

a precharge circuit for precharging, during a first time period, the capacitive device to an initial voltage thereacross, said first terminal of the capacitive device being coupled to a source of a first voltage and said second terminal of the capacitive device being coupled to a source of a second voltage;

a current path from the common node of the differential transistor pair to the first terminal of the capacitive device; and

a driver circuit responsive to a first control signal, for driving, with a first current during a second time period, the voltage of the second terminal of the capacitive device in a direction to capacitively couple the first terminal and, by way of the current path, the common node to respective voltages sufficient in magnitude and polarity to cause a current, substantially equal in magnitude to the first current, to flow collectively through one or both transistors of the differential transistor pair;

wherein the first current flows as a displacement current through the capacitive device and is projected onto the common node, thereby providing a dynamic tail current for the differential transistor pair substantially equal in magnitude to the first current;

said integrated circuit further comprising a second differential transistor pair; and

wherein

the capacitive device is disposed in close local proximity to, and also uniquely associated with, said differential transistor pair and said second differential transistor pair; and

said differential transistor pair and said second differential transistor pair each includes a respective gating circuit connecting the respective common node thereof to the first terminal of the capacitive device.

58. An integrated circuit comprising:

a first transistor and a second transistor configured as a differential transistor pair having a common node connecting respective first current handling terminals of each transistor within the pair;

a capacitive device having a first terminal and a second terminal;

a precharge circuit for precharging, during a first time period, the capacitive device to an initial voltage thereacross, said first terminal of the capacitive device being coupled to a source of a first voltage and said second terminal of the capacitive device being coupled to a source of a second voltage;

a current path from the common node of the differential transistor pair to the first terminal of the capacitive device; and

a driver circuit responsive to a first control signal, for driving, with a first current during a second time period, the voltage of the second terminal of the capacitive device in a direction to capacitively couple the first terminal and, by way of the current path, the common node to respective voltages sufficient in magnitude and polarity to cause a current, substantially equal in magnitude to the first current, to flow collectively through one or both transistors of the differential transistor pair;

wherein the first current flows as a displacement current through the capacitive device and is projected onto the common node, thereby providing a dynamic tail current for the differential transistor pair substantially equal in magnitude to the first current; and

wherein the current path consists of a direct wired connection between the common node and the first terminal of the capacitive device.

59. An integrated circuit comprising:

a first transistor and a second transistor configured as a differential transistor pair having a common node connecting respective first current handling terminals of each transistor within the pair;

a capacitive device having a first terminal and a second terminal;

a precharge circuit for precharging, during a first time period, the capacitive device to an initial voltage thereacross, said first terminal of the capacitive device being coupled to a source of a first voltage and said second terminal of the capacitive device being coupled to a source of a second voltage;

a current path from the common node of the differential transistor pair to the first terminal of the capacitive device; and

a driver circuit responsive to a first control signal, for driving, with a first current during a second time period, the voltage of the second terminal of the capacitive device in a direction to capacitively couple the first terminal and, by way of the current path, the common node to respective voltages sufficient in magnitude and polarity to cause a current, substantially equal in magnitude to the first current, to flow collectively through one or both transistors of the differential transistor pair;

wherein the first current flows as a displacement current through the capacitive device and is projected onto the common node, thereby providing a dynamic tail current for the differential transistor pair substantially equal in magnitude to the first current; and

wherein the current path includes at least one transistor connecting the common node to the first terminal of the capacitive device, which current path is enabled to conduct current therebetween at least during a time when the driver circuit is enabled by the first control signal.

60. An integrated circuit as in claim 59 wherein:

the current path includes no device configured to function as a constant current source during a time when the driver circuit is enabled by the first control signal; and

the magnitude of the first current is controlled by the driver circuit.

61. An integrated circuit as in claim 59 wherein:

the current path includes at least one device configured to function as a constant current source during a time when the driver circuit is enabled by the first control signal; and

the magnitude of the first current is controlled by the constant current source.

62. An integrated circuit comprising:

a first transistor and a second transistor configured as a differential transistor pair having a common node connecting respective first current handling terminals of each transistor within the pair;

a capacitive device having a first terminal and a second terminal;

a precharge circuit for precharging, during a first time period, the capacitive device to an initial voltage thereacross, said first terminal of the capacitive device being coupled to a source of a first voltage and said second terminal of the capacitive device being coupled to a source of a second voltage;

a current path from the common node of the differential transistor pair to the first terminal of the capacitive device; and

a driver circuit responsive to a first control signal, for driving, with a first current during a second time period, the voltage of the second terminal of the capacitive device in a direction to capacitively couple the first terminal and, by way of the current path, the common node to respective voltages sufficient in magnitude and polarity to cause a current, substantially equal in magnitude to the first current, to flow collectively through one or both transistors of the differential transistor pair;

wherein the first current flows as a displacement current through the capacitive device and is projected onto the common node, thereby providing a dynamic tail current for the differential transistor pair substantially equal in magnitude to the first current; and

wherein the differential transistor pair is incorporated within a linear amplifier circuit.

66. An integrated circuit as in claim 62 wherein the integrated circuit further comprises:

a pair of load devices, each respectively connected between a respective second current handling terminal of the differential transistor pair and a power supply terminal.

63. An integrated circuit comprising:

a first transistor and a second transistor configured as a differential transistor pair having a common node connecting respective first current handling terminals of each transistor within the pair;

a capacitive device having a first terminal and a second terminal;

a precharge circuit for precharging, during a first time period, the capacitive device to an initial voltage thereacross, said first terminal of the capacitive device being coupled to a source of a first voltage and said second terminal of the capacitive device being coupled to a source of a second voltage;

a current path from the common node of the differential transistor pair to the first terminal of the capacitive device; and

a driver circuit responsive to a first control signal, for driving, with a first current during a second time period, the voltage of the second terminal of the capacitive device in a direction to capacitively couple the first terminal and, by way of the current path, the common node to respective voltages sufficient in magnitude and polarity to cause a current, substantially equal in magnitude to the first current, to flow collectively through one or both transistors of the differential transistor pair;

wherein the first current flows as a displacement current through the capacitive device and is projected onto the common node, thereby providing a dynamic tail current for the differential transistor pair substantially equal in magnitude to the first current; and

wherein the differential transistor pair is incorporated within a latching amplifier circuit having a separate latch enable input.

64. An integrated circuit comprising:

a first transistor and a second transistor configured as a differential transistor pair having a common node connecting respective first current handling terminals of each transistor within the pair;

a capacitive device having a first terminal and a second terminal;

a precharge circuit for precharging, during a first time period, the capacitive device to an initial voltage thereacross, said first terminal of the capacitive device being coupled to a source of a first voltage and said second terminal of the capacitive device being coupled to a source of a second voltage;

a current path from the common node of the differential transistor pair to the first terminal of the capacitive device; and

a driver circuit responsive to a first control signal, for driving, with a first current during a second time period, the voltage of the second terminal of the capacitive device in a direction to capacitively couple the first terminal and, by way of the current path, the common node to respective voltages sufficient in magnitude and polarity to cause a current, substantially equal in magnitude to the first current, to flow collectively through one or both transistors of the differential transistor pair;

wherein the first current flows as a displacement current through the capacitive device and is projected onto the common node, thereby providing a dynamic tail current for the differential transistor pair substantially equal in magnitude to the first current; and

wherein the differential transistor pair is incorporated within a latching amplifier circuit having no separate latch enable input; and

wherein the latching amplifier circuit stores new information as a result of the differential output signal developed by the differential transistor pair during the second time period.

65. An integrated circuit as in claim 64 wherein the integrated circuit further comprises:

a pair of cross-coupled inverters configured as a latch, each inverter'"'"'s output respectively connected to the other inverter'"'"'s input and also connected to a respective second current handling terminal of the transistors within the differential transistor pair;

wherein the first control signal provides a strobe signal for the latch.

67. An integrated circuit comprising:

a first transistor and a second transistor configured as a differential transistor pair having a common node connecting respective first current handling terminals of each transistor within the pair;

a capacitive device having a first terminal and a second terminal;

a precharge circuit for precharging, during a first time period, the capacitive device to an initial voltage thereacross, said first terminal of the capacitive device being coupled to a source of a first voltage and said second terminal of the capacitive device being coupled to a source of a second voltage;

a current path from the common node of the differential transistor pair to the first terminal of the capacitive device; and

a driver circuit responsive to a first control signal, for driving, with a first current during a second time period, the voltage of the second. terminal of the capacitive device in a direction to capacitively couple the first terminal and, by way of the current path, the common node to respective voltages sufficient in magnitude and polarity to cause a current, substantially equal in magnitude to the first current, to flow collectively through one or both transistors of the differential transistor pair;

wherein the first current flows as a displacement current through the capacitive device and is projected onto the common node, thereby providing a dynamic tail current for the differential transistor pair substantially equal in magnitude to the first current; and

wherein the differential transistor pair is incorporated within an external input buffer of the integrated circuit.

68. An integrated circuit as in claim 67 wherein:

the first and second time periods are controlled to occur at respective times relative to an external clock signal operably received by the integrated circuit.

69. An integrated circuit as in claim 67 wherein:

a control terminal of one transistor of the differential transistor pair is coupled to receive an external input signal; and

a control terminal of the other transistor of the differential transistor pair is coupled to receive a reference voltage.

70. An integrated circuit as in claim 67 further comprising:

a control terminal of one transistor of the differential transistor pair is coupled to receive an external input signal; and

a control terminal of the other transistor of the differential transistor pair is coupled to receive a complementary external input signal.

71. An integrated circuit comprising:

a first transistor and a second transistor configured as a differential transistor pair having a common node connecting respective first current handling terminals of each transistor within the pair;

a capacitive device having a first terminal and a second terminal;

a precharge circuit for precharging, during a first time period, the capacitive device to an initial voltage thereacross, said first terminal of the capacitive device being coupled to a source of a first voltage and said second terminal of the capacitive device being coupled to a source of a second voltage;

a current path from the common node of the differential transistor pair to the first terminal of the capacitive device; and

a driver circuit responsive to a first control signal, for driving, with a first current during a second time period, the voltage of the second terminal of the capacitive device in a direction to capacitively couple the first terminal and, by way of the current path, the common node to respective voltages sufficient in magnitude and polarity to cause a current, substantially equal in magnitude to the first current, to flow collectively through one or both transistors of the differential transistor pair;

wherein the first current flows as a displacement current through the capacitive device and is projected onto the common node, thereby providing a dynamic tail current for the differential transistor pair substantially equal in magnitude to the first current; and

wherein the differential transistor pair is incorporated within an I/O bus line amplifier of a memory array within the integrated circuit.

72. An integrated circuit comprising:

a first transistor and a second transistor configured as a differential transistor pair having a common node connecting respective first current handling terminals of each transistor within the pair;

a capacitive device having a first terminal and a second terminal;

a precharge circuit for precharging, during a first time period, the capacitive device to an initial voltage thereacross, said first terminal of the capacitive device being coupled to a source of a first voltage and said second terminal of the capacitive device being coupled to a source of a second voltage;

a current path from the common node of the differential transistor pair to the first terminal of the capacitive device; and

a driver circuit responsive to a first control signal, for driving, with a first current during a second time period, the voltage of the second terminal of the capacitive device in a direction to capacitively couple the first terminal and, by way of the current path, the common node to respective voltages sufficient in magnitude and polarity to cause a current, substantially equal in magnitude to the first current, to flow collectively through one or both transistors of the differential transistor pair;

wherein the first current flows as a displacement current through the capacitive device and is projected onto the common node, thereby providing a dynamic tail current for the differential transistor pair substantially equal in magnitude to the first current; and

wherein the differential transistor pair is incorporated within a bit line read amplifier of a memory array within the integrated circuit.

76. An integrated circuit comprising:

a first transistor and a second transistor configured as a differential transistor pair having a common node connecting respective first current handling terminals of each transistor within the pair;

a capacitive device having a first terminal and a second terminal;

a precharge circuit for precharging, during a first time period, the capacitive device to an initial voltage thereacross, said first terminal of the capacitive device being coupled to a source of a first voltage and said second terminal of the capacitive device being coupled to a source of a second voltage;

a current path from the common node of the differential transistor pair to the first terminal of the capacitive device; and

a driver circuit responsive to a first control signal, for driving, with a first current during a second time period, the voltage of the second terminal of the capacitive device in a direction to capacitively couple the first terminal and, by way of the current path, the common node to respective voltages sufficient in magnitude and polarity to cause a current, substantially equal in magnitude to the first current, to flow collectively through one or both transistors of the differential transistor pair;

wherein the first current flows as a displacement current through the capacitive device and is projected onto the common node, thereby providing a dynamic tail current for the differential transistor pair substantially equal in magnitude to the first current;

wherein the driver circuit is arranged to drive the second terminal of the capacitive device toward a power supply voltage; and

wherein the driver circuit is arranged to drive the second terminal of the capacitive device with a constant current.

77. An integrated circuit as in claim 76 wherein the driver circuit comprises:

a switch transistor in series with a current source device, together coupled between the second terminal of the capacitive device and a power supply terminal operably coupled to receive the power supply voltage.

78. An integrated circuit as in claim 77 wherein the current source device comprises:

a transistor biased with a reference voltage coupled to the control terminal thereof.

80. An integrated circuit comprising:

a first transistor and a second transistor configured as a differential transistor pair having a common node connecting respective first current handling terminals of each transistor within the pair;

a capacitive device having a first terminal and a second terminal;

a precharge circuit for precharging, during a first time period, the capacitive device to an initial voltage thereacross, said first terminal of the capacitive device being coupled to a source of a first voltage and said second terminal of the capacitive device being coupled to a source of a second voltage;

a current path from the common node of the differential transistor pair to the first terminal of the capacitive device; and

a driver circuit responsive to a first control signal, for driving, with a first current during a second time period, the voltage of the second terminal of the capacitive device in a direction to capacitively couple the first terminal and, by way of the current path, the common node to respective voltages sufficient in magnitude and polarity to cause a current, substantially equal in magnitude to the first current, to flow collectively through one or both transistors of the differential transistor pair;

wherein the first current flows as a displacement current through the capacitive device and is projected onto the common node, thereby providing a dynamic tail current for the differential transistor pair substantially equal in magnitude to the first current;

wherein each transistor of the differential transistor pair comprises a field effect transistor and the common node comprises a common-source node;

wherein while the first current flows through the capacitive device as a displacement current, the first terminal of the capacitive device assumes a voltage at which the current collectively flowing through one or both transistors of the differential transistor pair remains substantially equal to the first current;

wherein the capacitive device comprises a field effect transistor connected to function as a capacitor and disposed in close local proximity to, and uniquely associated with, the differential transistor pair; and

wherein the current path includes at least one transistor connecting the common node to the first terminal of the capacitive device, which transistor is enabled to conduct current therebetween at least during a time when the driver circuit is enabled by the first control signal.

81. An integrated circuit as in claim 80 wherein:

the differential transistor pair is incorporated within an external input buffer of the integrated circuit;

a control terminal of one transistor of the differential transistor pair is coupled to receive an external input signal; and

a control terminal of the other transistor of the differential transistor pair is coupled to receive a reference voltage.

82. An integrated circuit as in claim 80 wherein:

the differential transistor pair is incorporated within an external input buffer of the integrated circuit;

a control terminal of one transistor of the differential transistor pair is coupled to receive an external input signal; and

a control terminal of the other transistor of the differential transistor pair is coupled to receive a complementary external input signal.

83. An integrated circuit as in claim 80 wherein the driver circuit comprises:

a switch transistor in series with a current source device, together coupled between the second terminal of the capacitive device and a power supply terminal.

84. In an integrated circuit including a first NMOS transistor and a second NMOS transistor configured as a differential transistor pair and having commonly-connected source terminals, said differential transistor pair for developing a differential current in response to a differential voltage applied between the respective gate terminals of the first and second NMOS transistors, a method of providing a tail current through the differential transistor pair, said method comprising:

precharging a capacitive device by coupling a first terminal thereof to a first voltage and coupling a second terminal thereof to a second voltage higher than the first voltage;

then

driving, with a substantially constant first current, the second terminal of the precharged capacitive device toward a lower voltage, thereby tending to capacitively couple the first terminal of the capacitive device toward a voltage below the first voltage; and

providing a current path from the common source node to the first terminal of the capacitive device at least during a time when the first terminal if capacitively coupled toward a lower voltage;

wherein the first terminal and, by way of the current path, the common node assume respective voltages sufficiently low to cause a current, substantially equal to the first current, to flow collectively through one or both transistors of the differential transistor pair; and

wherein the first current flows as a displacement current through the capacitive device and is projected onto the common node, thereby providing a dynamic tail current for the differential transistor pair substantially equal in magnitude to the first current.

85. A method as in claim 84 wherein:

for certain values of input voltages applied to the differential transistor pair, certain transistor characteristics of the differential transistor pair, and certain magnitudes of the first current, the voltage assumed by the common source node is below the lowest power supply voltage operably received by the integrated circuit.

86. In an integrated circuit including a first NMOS transistor and a second NMOS transistor configured as a differential transistor pair and having commonly-connected source terminals, said differential transistor pair for developing a differential current in response to a differential voltage applied between the respective gate terminals of the first and second NMOS transistors, a method of providing a tail current through the differential transistor pair, said method comprising:

precharging a capacitive device by coupling a first terminal thereof to a first voltage and coupling a second terminal thereof to a second voltage higher than the first voltage;

then

driving, with a controlled first current, the second terminal of the precharged capacitive device toward a lower voltage, thereby tending to capacitively couple the first terminal of the capacitive device toward a voltage below the first voltage; and

providing a current path from the common source node to the first terminal of the capacitive device at least during a time when the first terminal is capacitively coupled toward a lower voltage;

wherein the first terminal and, by way of the current path, the common node assume respective voltages sufficiently low to cause a current, substantially equal to the first current, to flow collectively through one or both transistors of the differential transistor pair;

wherein the first current flows as a displacement current through the capacitive device and is projected onto the common node, thereby providing a dynamic tail current for the differential transistor pair substantially equal in magnitude to the first current; and

wherein for certain values of input voltages applied to the differential transistor pair, certain transistor characteristics of the differential transistor pair, and certain magnitudes of the first current, the voltage assumed by the common source node is above the lowest power supply voltage operably received by the integrated circuit.