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Digitally programmable phase-lock loop for high-speed data communications

  • US 6,462,594 B1
  • Filed: 11/08/2000
  • Issued: 10/08/2002
  • Est. Priority Date: 11/08/2000
  • Status: Expired due to Term
First Claim
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1. A programmable phase-locked loop comprising:

  • a reference-clock input;

    a program input for receiving a program signal associated with one or more bits;

    a phase-frequency detector having first and second inputs and an output, with the first input coupled to the reference-clock input;

    a programmable charge pump having a first input coupled to the output of the phase-frequency detector, a second input coupled to the program input, and an output for producing a current based on signals at the first input and the second input, the current being substantially proportional to the program signal;

    a programmable loop filter having a first input coupled to the output of the charge pump, and a second input coupled to the program input to adjust a characteristic frequency response of the loop filter, the characteristic frequency response being substantially proportional to the program signal; and

    a programmable oscillator having a first input coupled to the programmable loop filter, a second input coupled to the program input, and an output coupled to the phase-frequency detector for producing an oscillating signal having a frequency based on the signals at its input and the program input, the programmable oscillator having a gain substantially proportional to the program signal.

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