Digitally programmable phase-lock loop for high-speed data communications

• US 6,462,594 B1
• Filed: 11/08/2000
• Issued: 10/08/2002
• Est. Priority Date: 11/08/2000
• Status: Expired due to Term

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Robinson, Moises E., Grung, Bernard L.
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): Nguyen, Hai L.
• Application Number:
  US09/708,695
• Time in Patent Office: 699 Days
• Field of Search: 327/156, 327/157, 327/147, 327/148, 327/150, 327/149, 327/158, 331/172, 331/175, 331/DIG.2, 375/374, 375/375, 375/376
• US Class Current: 327/159
• CPC Class Codes: H03L 2207/04 Modifications for maintaining constant the phase-locked loop damping factor when other loop parameters change
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/0898 the source or sink current values being variable H03L7/0896 takes precedence
• CPC Class Codes: H03L 7/0995 the oscillator comprising a ring oscillator
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence
• CPC Class Codes: H04L 7/0008 Synchronisation information channels, e.g. clock distribution lines
• CPC Class Codes: H04L 7/02 Speed or phase control by the received code signals, the signals containing no special synchronisation information H04L7/0075 takes precedence

Abstract

Electronic devices are typically coupled together to operate as systems that require the communication of data between two or more devices. Many of these devices includes a communications circuit, such as receiver, transmitter, or transceiver for this purpose. A typical component in these communication circuits is the phase-lock loop, a circuit that in receiver circuits determines the timing of pulses in a received data signal and in transmitter circuits clocks the data out at a predetermined rate. One problem with phase-lock loops and thus the receiver and transmitter circuits that incorporate them is that they are generally tuned, or tailored, to operate at a certain frequency. This means that one cannot generally use a receiver or transmitter circuit having phase-lock loops tuned for one frequency to communicate at another frequency. The inability to communicate at other frequencies limits the usefulness of not only the receiver and transmitter circuits but also their electronic devices. Accordingly, the present inventors devised a digitally programmable phase-lock loop which operates at a frequency selected from a set of two of more frequencies. One such phase-lock loop includes a charge pump, a loop filter, and a voltage-controlled oscillator, all of which are programmable to control the operating frequency of the phase-lock loop and thus devices, such as receivers, transmitters, and transceivers incorporating it. Moreover, the programmability of these three components enables the exemplary embodiment to maintains a constant damping factor and a constant ratio of input frequency to loop bandwidth for each frequency setting, thereby promoting loop stability and rapid settling at each selected frequency.

Claims

1. A programmable phase-locked loop comprising:

a reference-clock input;

a program input for receiving a program signal associated with one or more bits;

a phase-frequency detector having first and second inputs and

an output, with the first input coupled to the

reference-clock input;

a programmable charge pump having a first input coupled to the output of the phase-frequency detector, a second input coupled to the program input, and an output for producing a current based on signals at the first input and the second input, the current being substantially proportional to the program signal;

a programmable loop filter having a first input coupled to the output of the charge pump, and a second input coupled to the program input to adjust a characteristic frequency response of the loop filter, the characteristic frequency response being substantially proportional to the program signal; and

a programmable oscillator having a first input coupled to the programmable loop filter, a second input coupled to the program input, and an output coupled to the phase-frequency detector for producing an oscillating signal having a frequency based on the signals at its input and the program input, the programmable oscillator having a gain substantially proportional to the program signal.

2. The programmable phase-locked loop of claim 1, further comprising:

a frequency divider coupled between the output of the programmable oscillator and the second input of the phase-frequency detector.

3. The programmable phase-locked loop of claim 1, wherein the programmable loop filter includes a programmable resistance responsive to the program signal at the program input.

4. The programmable phase-locked loop of claim 1, wherein the programmable oscillator comprises a programmable voltage-controlled oscillator.

5. The phase-locked loop of claim 1, wherein the program signal comprises a digital word including two or more bits.

6. An integrated circuit comprising:

a reference-clock input;

a program input for receiving a program signal associated with one or more bits;

a phase-frequency detector having first and second inputs and an output, with the first input coupled to the reference-clock input;

a programmable charge pump having a first input coupled to the output of the phase-frequency detector, a second input coupled to the program input, and an output for producing a current based on signals at the first input and the second input, the current being substantially proportional to the program signal;

a programmable loop filter having a first input coupled to the output of the charge pump, and a second input coupled to the program input to adjust a characteristic frequency response of the loop filter, the characteristic frequency response being substantially proportional to the program signal; and

a programmable oscillator having a first input coupled to the programmable loop filter, a second input coupled to the program input, and an output coupled to the phase-frequency detector for producing an oscillating signal having a frequency based on the signals at its input and the program input, the programmable oscillator having a gain substantially proportional to the program signal.

7. A phase-locked loop comprising:

a reference-clock input;

a program input for receiving a program signal associated with one or more bits;

a phase-frequency detector having first and second inputs and an output, with the first input coupled to the reference-clock input;

a programmable charge pump having a first input coupled to the output of the phase-frequency detector, a second input coupled to the program input, and an output for producing a current based on signals at the first input and the second input,

a programmable loop filter having a first input coupled to the output of the charge pump, and a second input coupled to the program input to adjust a characteristic frequency response of the loop filter;

a programmable oscillator having a first input coupled to the programmable loop filter, a second input coupled to the program input, and an output coupled to the phase-frequency detector for producing an oscillating signal having a frequency based on the signals at its first input and the program input;

means for maintaining a constant damping factor; and

means for maintaining a constant ratio of input frequency to loop bandwidth.

8. An integrated circuit comprising:

a reference-clock input;

a program input for receiving a program signal associated with one or more bits;

a phase-frequency detector having first and second inputs and an output, with the first input coupled to the reference-clock input;

a programmable charge pump having a first input coupled to the output of the phase-frequency detector, a second input coupled to the program input, and an output for producing a current based on signals at the first input and the second input;

a programmable loop filter having a first input coupled to the output of the charge pump, and a second input coupled to the program input to adjust a characteristic frequency response of the loop filter;

a programmable oscillator having a first input coupled to the programmable loop filter, a second input coupled to the program input, and an output coupled to the phase-frequency detector for producing an oscillating signal having a frequency based on the signals at its first input and the program input;

means for maintaining a constant damping factor; and

means for maintaining a constant ratio of input frequency to loop bandwidth.