Low current redundancy anti-fuse apparatus

• US 6,462,608 B2
• Filed: 07/18/1997
• Issued: 10/08/2002
• Est. Priority Date: 10/03/1996
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Ho, Fan, Beigel, Kurt D., Cutter, Douglas J.
• Primary Examiner(s): Cunningham, Terry D.
• Application Number:
  US08/896,490
• Publication Number:
  US 20010013805A1
• Time in Patent Office: 1,908 Days
• Field of Search: 327/526, 327/525, 365/96
• US Class Current: 327/525
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 29/785 with redundancy programming schemes
• CPC Class Codes: G11C 29/83 with reduced power consumption

Abstract

A programmable circuit includes a first node and provides a programmed signal based on the state of the first node. A first anti-fuse has a programmed state and an unprogrammed state and couples the first node to a first power supply when in the programmed state and decouples the first node from the first power supply when in the unprogrammed state. A second anti-fuse has a programmed state and an unprogrammed state and couples the first node to a second power supply when in the programmed state and decouples the first node from the second power supply when in the unprogrammed state. The state of the programmed signal can be used to replace a primary circuit element of an integrated circuit with a redundant circuit element.

Claims

1. A programmable circuit coupled to a first power supply and a second power supply for providing a programmed signal in an integrated circuit, comprising:

a first node, wherein the state of the programmed signal is based on the state of the first node;

a first anti-fuse having a programmed state and an unprogrammed state and coupling the first node to the first power supply when in the programmed state and decoupling the first node from the first power supply when in the unprogrammed state, wherein the first anti-fuse has a first terminal coupled to the first node and a second terminal;

a second anti-fuse having a programmed state and an unprogrammed state and coupling the first node to the second power supply when in the programmed state and decoupling the first node from the second power supply when in the unprogrammed state, wherein the second anti-fuse has a first terminal coupled to the first node and a second terminal;

a first programming bus carrying a sufficient voltage to short the first anti-fuse;

a first switch coupled to the second terminal of the first anti-fuse for coupling the second terminal of the first anti-fuse to the first power supply during normal operation of the integrated circuit and coupling the second terminal of the first anti-fuse to the first programing bus during a first programming operation of the integrated circuit for programming the first anti-fuse;

a second programming bus carrying a sufficient voltage to short the second anti-fuse;

a second switch coupled to the second terminal of the second anti-fuse for coupling the second terminal of the second anti-fuse to the second power supply during normal operation of the integrated circuit and coupling the second terminal of the second anti-fuse to the second programing bus during a second programming operation of the integrated circuit for programming the second anti-fuse; and

a third switch coupled between the second power supply and the first node and responsive to a plurality of programming control signals, wherein the third switch is closed to couple the first node to the second power supply during a programming operation of the integrated circuit and open during normal operations of the integrated circuit.

2. The programmable circuit of claim 1, wherein the third switch comprises two transistors.

3. The programmable circuit of claim 1, wherein the second power supply is a ground potential.

4. The programmable circuit of claim 1, wherein the third switch comprises a first transistor and a second transistor, wherein a gate of the first transistor is responsive to an enable signal, and wherein a gate of the second transistor is responsive to a further signal.

5. The programmable circuit of claim 4, wherein the first transistor is connected in parallel with the second transistor.

6. The programmable circuit of claim 5, wherein drains of the first and second transistors are connected to ground.

7. The programmable circuit of claim 4, wherein the gate of the second transistor is connected to a logic gate that is responsive to a plurality of control signals.

8. The programmable circuit of claim 7, wherein the plurality of control signals include at least one of a fuse bank select signal, a test mode signal, and an address input signal.

9. The programmable circuit of claim 7, wherein the plurality of control signals include a fuse bank select signal, a test mode signal, and an address input signal.

10. A programmable circuit for providing a programmed signal in an integrated circuit, comprising:

a first node, wherein the state of the programmed signal is based on the state of the first node;

a first anti-fuse having a first terminal and a second terminal and having a programmed state and an unprogrammed state, wherein the first terminal is coupled to the first node;

a second anti-fuse having a first terminal and a second terminal and having a programmed state and an unprogrammed state, wherein the first terminal is coupled to the first node;

a first programming bus carrying a sufficient voltage to short the first anti-fuse;

a first switch coupled to the second terminal of the first anti-fuse for coupling the second terminal of the first anti-fuse to a first power supply during normal operation of the integrated circuit and coupling the second terminal of the first anti-fuse to the first programing bus during a first programming operation of the integrated circuit for programming the first anti-fuse;

a second programming bus carrying a sufficient voltage to short the second anti-fuse;

a second switch coupled to the second terminal of the second anti-fuse for coupling the second terminal of the second anti-fuse to a second power supply during normal operation of the programmable circuit and coupling the second terminal of the second anti-fuse to the second programing bus during a second programming operation of the programmable circuit for programming the second anti-fuse;

wherein the first anti-fuse couples the first node to the first power supply during normal operation when in the programmed state and decouples the first node from the first power supply when in the unprogrammed state;

wherein the second anti-fuse couples the first node to the second power supply during normal operation when in the programmed state and decouples the first node from the second power supply when in the unprogrammed state; and

a third switch coupled between the second power supply and the first node and responsive to a plurality of programming control signals, wherein the third switch is closed to couple the first node to the second power supply during a programming operation of the integrated circuit and open during normal operations of the integrated circuit.

11. The programmable circuit of claim 10, wherein the second power supply comprises a ground node.

12. The programmable circuit of claim 10, wherein the third switch comprises two transistors.

13. The programmable circuit of claim 10, wherein the third switch comprises a first transistor and a second transistor, wherein a gate of the first transistor is responsive to an enable signal, and wherein a gate of the second transistor is responsive to a further signal.

14. The programmable circuit of claim 13, wherein the first transistor is connected in parallel with the second transistor.

15. The programmable circuit of claim 14, wherein drains of the first and second transistors are connected to ground.

16. The programmable circuit of claim 13, wherein the gate of the second transistor is connected to a logic gate that is responsive to a plurality of control signals.

17. The programmable circuit of claim 16, wherein the plurality of control signals include at least one of a fuse bank select signal, a test mode signal, and an address input signal.

18. The programmable circuit of claim 16, wherein the plurality of control signals include a fuse bank select signal, a test mode signal, and an address input signal.

19. A programmable circuit for providing a programmed signal in an integrated circuit, comprising:

a first node, wherein the state of the programmed signal is based on the state of the first node;

a first anti-fuse having a programmed state and an unprogrammed state and coupling the first node to a first power supply when in the programmed state and decoupling the first node from the first power supply when in the unprogrammed state;

a first programming circuit operably connected to the first anti-fuse for selectively changing the first anti-fuse from the unprogrammed state to the programmed state;

a second anti-fuse having a programmed state and an unprogrammed state and coupling the first node to a second power supply when in the programmed state and decoupling the first node from the second power supply when in the unprogrammed state;

a second programming circuit operably connected to the second anti-fuse for selectively changing the second anti-fuse from the unprogrammed state to the programmed state; and

a switch coupled between the second power supply and the first node, wherein the switch, when closed, couples the first node to the second power supply regardless of the state of the second anti-fuse, and wherein the switch is responsive to a plurality of input signals.

20. The programmable circuit of claim 19, wherein the second power supply comprises a ground node.

21. A programmable circuit for providing a programmed signal in an intergrated circuit, comprising:

a first node, wherein the state of the programmed signal is based on the state of the first node;

a first anti-fuse having a programmed state and an unprogrammed state and coupling the first node to a first power supply when in the programmed state and decoupling the first node from the first power supply when in the unprogrammed state;

a first programming circuit operably connected to the first anti-fuse for selectively changing the first anti-fuse from the unprogrammed state to the programmed state;

a second anti-fuse having a programmed state and an unprogrammed state and coupling the first node to a second power supply when in the programmed state and decoupling the first node from the second power supply when in the unprogrammed state;

a second programming circuit operably connected to the second anti-fuse for selectively changing the second anti-fuse from the unprogrammed state to the programmed state; and

a switch coupled between the second power supply and the first node, wherein the switch, when closed, couples the first node to the second power supply regardless of the state of the second anti-fuse, and wherein the switch is responsive to a plurality of input signals, wherein the switch comprises two transistors.

22. A programmable circuit for providing a programmed signal in an integrated circuit, comprising:

a first node, wherein the state of the programmed signal is based on the state of the first node;

a first anti-fuse having a programmed state and an unprogrammed state and coupling the first node to a first power supply when in the programmed state and decoupling the first node from the first power supply when in the unprogrammed state;

a first programming circuit operably connected to the first anti-fuse for selectively changing the first anti-fuse from the unprogrammed state to the programmed state;

a second anti-fuse having a programmed state and an unprogrammed state and coupling the first node to a second power supply when in the programmed state and decoupling the first node from the second power supply when in the unprogrammed state;

a second programming circuit operably connected to the second anti-fuse for selectively changing the second anti-fuse from the unprogrammed state to the programmed state; and

a switch coupled between the second power supply and the first node, wherein the switch, when closed, couples the first node to the second power supply regardless of the state of the second anti-fuse, and wherein the switch is responsive to a plurality of input signals, wherein the switch comprises a first transistor and a second transistor, wherein a gate of the first transistor is responsive to an enable signal, and wherein a gate of the second transistor is responsive to a further signal.

23. The programmable circuit of claim 22, wherein the first transistor is connected in parallel with the second transistor.

24. The programmable circuit of claim 23, wherein drains of the first and second transistors are both connected to ground.

25. The programmable circuit of claim 22, wherein the gate of the second transistor is connected to a logic gate that is responsive to a plurality of control signals.

26. The programmable circuit of claim 25, wherein the plurality of control signals include at least one of a fuse bank select signal, a test mode signal, and an address input signal.

27. The programmable circuit of claim 25, wherein the plurality of control signals include a fuse bank select signal, a test mode signal, and an address input signal.

28. A programmable circuit for providing a programmed signal in an integrated circuit, comprising:

a first node, wherein the state of the programmed signal is based on the state of the first node;

a first anti-fuse having a programmed state and an unprogrammed state and coupling the first node to a first power supply when in the programmed state and decoupling the first node from the first power supply when in the unprogrammed state;

a second anti-fuse having a programmed state and an unprogrammed state and coupling the first node to a second power supply when in the programmed state and decoupling the first node from the second power supply when in the unprogrammed state;

a first switch coupled between the second power supply and the first node and responsive to at least one programming control signal, wherein the switch is closed to couple the first node to the second power supply during a programming operation of the integrated circuit regardless of the state of the second anti-fuse and open during normal operation of the integrated circuit;

a second switch coupled between the second power supply and the first node and responsive to an enable signal, wherein the switch is closed to couple the first node to the second power supply based on the enable signal being in a first state regardless of the state of the second anti-fuse, and wherein the switch is open based on the enable signal being in a second state; and

a third switch coupled between the second power supply and the first node and responsive to a plurality of programming control signals.

29. The programmable circuit of claim 28, wherein the third switch is closed to couple the first node to the second power supply during a programming operation of the integrated circuit and open during normal operations of the integrated circuit.

30. The programmable circuit of claim 28, wherein the first switch and second switch each comprise a transistor.

31. The programmable circuit of claim 28, wherein the second power supply comprises a ground node.

32. The programmable circuit of claim 28, wherein the third switch comprises a first transistor and a second transistor, wherein a gate of the first transistor is responsive to an enable signal, and wherein a gate of the second transistor is responsive to a further signal.

33. The programmable circuit of claim 32, wherein the first transistor is connected in parallel with the second transistor.

34. The programmable circuit of claim 33, wherein drains of the first and second transistors are connected to ground.

35. The programmable circuit of claim 32, wherein the gate of the second transistor is connected to a logic gate that is responsive to a plurality of control signals.

36. The programmable circuit of claim 35, wherein the plurality of control signals include at least one of a fuse bank select signal, a test mode signal, and an address input signal.

37. The programmable circuit of claim 35, wherein the plurality of control signals include a fuse bank select signal, a test mode signal, and an address input signal.

38. A programmable circuit coupled to a first power supply and a second power supply for providing a programmed signal in an integrated circuit comprising:

a first node, wherein the state of the programmed signal is based on the state of the first node;

a first anti-fuse having a programmed state and an unprogrammed state and connected for coupling the first node to the first power supply when in the programmed state and decoupling the first node from the first power supply when in the unprogrammed state, wherein the first anti-fuse has a first terminal coupled to the first node and a second terminal;

a second anti-fuse having a programmed state and an unprogrammed state and connected for coupling the first node to the second power supply when in the programmed state and decoupling the first node from the second power supply when in the unprogrammed state, wherein the second anti-fuse has a first terminal coupled to the first node and a second terminal;

a first programming bus carrying a sufficient voltage to short the first anti-fuse;

a first switch coupled to the second terminal of the first anti-fuse for coupling the second terminal of the first anti-fuse to the first power supply during normal operation of the integrated circuit and coupling the second terminal of the first anti-fuse to the first programing bus during a first programming operation of the integrated circuit for programming the first anti-fuse;

a second programming bus carrying a sufficient voltage to short the second anti-fuse;

a second switch coupled to the second terminal of the second anti-fuse for coupling the second terminal of the second anti-fuse to the second power supply during normal operation of the integrated circuit and coupling the second terminal of the second anti-fuse to the second programing bus during a second programming operation of the integrated circuit for programming the second anti-fuse;

a first transistor coupled between the second power supply and the first node and responsive to a first at least one programming control signal; and

a second transistor coupled between the second power supply and the first node and responsive to a second at least one programming control signal.

39. The programmable circuit of claim 38, wherein the first transistor is closed to couple the first node to the second power supply during a programming operation of the integrated circuit and open during normal operations of the integrated circuit.

40. The programmable circuit of claim 38, wherein the second transistor is closed to couple the first node to the second power supply during a programming operation of the integrated circuit and open during normal operations of the integrated circuit.

41. The programmable circuit of claim 38, wherein the first programming control signal is an enable signal.

42. The programmable circuit of claim 38, wherein the second power supply comprises a source of ground potential.

43. The programmable circuit of claim 42, wherein the first power supply has a voltage V_cc.

44. The programmable circuit of claim 38, wherein the second programming control signal include at least one of a fuse bank select signal, a test mode signal, and an address input signal.

45. The programmable circuit of claim 38, wherein the second programming control signal include a fuse bank select signal, a test mode signal, and an address input signal.

46. A programmable circuit coupled to a first power supply and a second power supply for providing a programmed signal in an integrated circuit, comprising:

a first node, wherein the state of the programmed signal is based on the state of the first node;

a first anti-fuse having a programmed state and an unprogrammed state and connected for coupling the first node to the first power supply when in the programmed state and decoupling the first node from the first power supply when in the unprogrammed state, wherein the first anti-fuse has a first terminal coupled to the first node and a second terminal;

a second anti-fuse having a programmed state and an unprogrammed state and connected for coupling the first node to the second power supply when in the programmed state and decoupling the first node from the second power supply when in the unprogrammed state, wherein the second anti-fuse has a first terminal coupled to the first node and a second terminal;

a first programming bus carrying a sufficient voltage to short the first anti-fuse;

a first switch coupled to the second terminal of the first anti-fuse for coupling the second terminal of the first anti-fuse to the first power supply during normal operation of the integrated circuit and coupling the second terminal of the first anti-fuse to the first programing bus during a first programming operation of the integrated circuit for programming the first anti-fuse;

a second programming bus carrying a sufficient voltage to short the second anti-fuse; and

a second switch coupled to the second terminal of the second anti-fuse for coupling the second terminal of the second anti-fuse to the second power supply during normal operation of the integrated circuit and coupling the second terminal of the second anti-fuse to the second programing bus during a second programming operation of the integrated circuit for programming the second anti-fuse; and

a third switch comprising a first transistor coupled between the second power supply and the first node and responsive to an enable signal, the third switch further comprising a second transistor coupled between the second power supply and the first node and responsive to a further signal.

47. The programming circuit of claim 46, wherein the first transistor is closed to couple the first node to the second power supply based on the enable signal being in a first state, and wherein the first transistor is open based on the enable signal being in a second state.

48. The programming circuit of claim 46, wherein the second transistor is closed to couple the first node to the second power supply based on the further signal being in a first state, and wherein the second transistor is open based on the further signal being in a second state.

49. The programming circuit of claim 48, wherein the further signal is based on a state of at least one of a fuse bank select signal, a test mode signal, and an address input signal.

50. The programmable circuit of claim 48, wherein the further signal is based on a state of a fuse bank select signal, a state of a test mode signal, and a state of an address input signal.

51. The programmable circuit according to claim 46, wherein the second power supply comprises a source of ground potential.

52. The programmable circuit according to claim 46, wherein the first power supply has a voltage V_cc.

53. A programmable circuit for providing a programmed signal in an integrated circuit, comprising:

a first node, wherein the state of the programmed signal is based on the state of the first node;

a first anti-fuse having a first terminal and a second terminal and having a programmed state and an unprogrammed state, wherein the first terminal is coupled to the first node and couples the first node to the first power supply during normal operation when in the programmed state and decouples the first node from the first power supply when in the unprogrammed state;

a second anti-fuse having a first terminal and a second terminal and having a programmed state and an unprogrammed state, wherein the first terminal is coupled to the first node and couples the first node to the second power supply during normal operation when in the programmed state and decouples the first node from the second power supply when in the unprogrammed state;

a first programming bus carrying a sufficient voltage to short the first anti-fuse;

a first switch coupled to the second terminal of the first anti-fuse for selectively coupling the second terminal of the first anti-fuse to a first power supply during normal operation of the integrated circuit and coupling the second terminal of the first anti-fuse to the first programing bus during a first programming operation of the integrated circuit for programming the first anti-fuse;

a second programming bus carrying a sufficient voltage to short the second anti-fuse;

a second switch coupled to the second terminal of the second anti-fuse for selectively coupling the second terminal of the second anti-fuse to a second power supply during normal operation of the programmable circuit and coupling the second terminal of the second anti-fuse to the second programing bus during a second programming operation of the programmable circuit for programming the second anti-fuse;

wherein only one of the first and second anti-fuses is in the programmed state during normal operation; and

a third switch coupled between the second power supply and the first node and responsive to a plurality of programming control signals, wherein the third switch is closed to couple the first node to the second power supply during a programming operation of the integrated circuit and open during normal operations of the integrated circuit.

54. The programmable circuit according to claim 53, wherein the second power supply is a source of ground potential.

55. The programmable circuit according to claim 53, wherein the first power supply has a voltage V_cc.

56. A programmable circuit for providing a programmed signal in an integrated circuit, comprising:

a first node, wherein the state of the programmed signal is based on the state of the first node;

a first anti-fuse having a programmed state and an unprogrammed state and selectively coupling the first node to a first power supply when in the programmed state and decoupling the first node from the first power supply when in the unprogrammed state;

a second anti-fuse having a programmed state and an unprogrammed state and selectively coupling the first node to a second power supply when in the programmed state and decoupling the first node from the second power supply when in the unprogrammed state;

a first switch coupled between the second power supply and the first node and responsive to at least one programming control signal, wherein the switch is closed to couple the first node to the second power supply during a programming operation of the integrated circuit regardless of the state of the second anti-fuse and open during normal operation of the integrated circuit;

a second switch coupled between the second power supply and the first node and responsive to an enable signal, wherein the switch is closed to couple the first node to the second power supply based on the enable signal being in a first state regardless of the state of the second anti-fuse, and wherein the switch is open based on the enable signal being in a second state;

wherein the only one of the first and second anti-fuses is put in the programmed state at the same time; and

a third switch coupled between the second power supply and the first node and responsive to a plurality of programming control signals, wherein the third switch is closed to couple the first node to the second power supply during a programming operation of the integrated circuit and open during normal operations of the integrated circuit.

57. The programmable circuit according to claim 56, wherein the second power supply is a source of ground potential.

58. The programmable circuit according to claim 56, wherein the first power supply has a voltage V_cc.

59. A programmable circuit coupled to a first power supply and a second power supply for providing a programmed signal in an integrated circuit, comprising:

a first node, wherein the state of the programmed signal is based on the state of the first node;

a first anti-fuse having a programmed state and an unprogrammed state and coupling the first node to the first power supply when in the programmed state and decoupling the first node from the first power supply when in the unprogrammed state, wherein the first anti-fuse has a first terminal coupled to the first node and a second terminal;

a second anti-fuse having a programmed state and an unprogrammed state and coupling the first node to the second power supply when in the programmed state and decoupling the first node from the second power supply when in the unprogrammed state, wherein the second anti-fuse has a first terminal coupled to the first node and a second terminal;

a first programming bus carrying a sufficient voltage to short the first anti-fuse;

a first switch coupled to the second terminal of the first anti-fuse for coupling the second terminal of the first anti-fuse to the first power supply during normal operation of the integrated circuit and coupling the second terminal of the first anti-fuse to the first programing bus during a first programming operation of the integrated circuit for programming the first anti-fuse;

a second programming bus carrying a sufficient voltage to short the second anti-fuse;

a second switch coupled to the second terminal of the second anti-fuse for coupling the second terminal of the second anti-fuse to the second power supply during normal operation of the integrated circuit and coupling the second terminal of the second anti-fuse to the second programing bus during a second programming operation of the integrated circuit for programming the second anti-fuse; and

a third switch coupled between the second power supply and the first node and responsive to a plurality of programming control signals, wherein the third switch includes two transistors.

60. The programming circuit of claim 59, wherein the third switch is closed to couple the first node to the second power supply during a programming operation of the integrated circuit and open during normal operations of the integrated circuit.

61. The programmable circuit of claim 59, wherein the second power supply is a ad ground potential.

62. The programmable circuit of claim 59, wherein a gate of a first of the two transistors is responsive to an enable signal, and wherein a gate of a second of the two transistors is responsive to a further signal.

63. The programmable circuit of claim 62, wherein the first transistor is connected in parallel with the second transistor.

64. The programmable circuit of claim 63, wherein drains of the first and second transistors are connected to ground.

65. The programmable circuit of claim 62, wherein the gate of the second transistor is connected to a logic gate that produces the further signal in response to a plurality of control signals.

66. The programmable circuit of claim 65, wherein the plurality of control signals include at least one of a fuse bank select signal, a test mode signal, and an address input signal.

67. The programmable circuit of claim 65, wherein the plurality of control signals include a fuse bank select signal, a test mode signal, and an address input signal.

68. A programmable circuit for providing a programmed signal in an integrated circuit, comprising:

a first node, wherein the state of the programmed signal is based on the state of the first node;

a first anti-fuse having a first terminal and a second terminal and having a programmed state and an unprogrammed state, wherein the first terminal is coupled to the first node;

a second anti-fuse having a first terminal and a second terminal and having a programmed state and an unprogrammed state, wherein the first terminal is coupled to the first node;

a first programming bus carrying a sufficient voltage to short the first anti-fuse;

a first switch coupled to the second terminal of the first anti-fuse for coupling the second terminal of the first anti-fuse to a first power supply during normal operation of the integrated circuit and coupling the second terminal of the first anti-fuse to the first programing bus during a first programming operation of the integrated circuit for programming the first anti-fuse;

a second programming bus carrying a sufficient voltage to short the second anti-fuse;

a second switch coupled to the second terminal of the second anti-fuse for coupling the second terminal of the second anti-fuse to a second power supply during normal operation of the programmable circuit and coupling the second terminal of the second anti-fuse to the second programing bus during a second programming operation of the programmable circuit for programming the second anti-fuse;

wherein the first anti-fuse couples the first node to the first power supply during normal operation when in the programmed state and decouples the first node from the first power supply when in the unprogrammed state;

wherein the second anti-fuse couples the first node to the second power supply during normal operation when in the programmed state and decouples the first node from the second power supply when in the unprogrammed state; and

a third switch coupled between the second power supply and the first node and responsive to a plurality of programming control signals, wherein the third switch includes two transistors.

69. The programmable circuit of claim 68, wherein the third switch is closed to couple the first node to the second power supply during a programming operation of the integrated circuit and open during normal operations of the integrated circuit.

70. The programmable circuit of claim 68, wherein the second power supply comprises a ground node.

71. The programmable circuit of claim 68, wherein a gate of a first of the two transistors is responsive to an enable signal, and wherein a gate of a second of the two transistors is responsive to a further signal.

72. The programmable circuit of claim 71, wherein the first transistor is connected in parallel with the second transistor.

73. The programmable circuit of claim 72, wherein drains of the first and second transistors are connected to ground.

74. The programmable circuit of claim 71, wherein the gate of the second transistor is connected to a logic gate that is responsive to a plurality of control signals.

75. The programmable circuit of claim 74, wherein the plurality of control signals include at least one of a fuse bank select signal, a test mode signal, and an address input signal.

76. The programmable circuit of claim 74, wherein the plurality of control signals include a fuse bank select signal, a test mode signal, and an address input signal.

77. A programmable circuit for providing a programmed signal in an integrated circuit, comprising:

a first node, wherein the state of the programmed signal is based on the state of the first node;

a first anti-fuse having a programmed state and an unprogrammed state and coupling the first node to a first power supply when in the programmed state and decoupling the first node from the first power supply when in the unprogrammed state;

a first programming circuit operably connected to the first anti-fuse for selectively changing the first anti-fuse from the unprogrammed state to the programmed state;

a second anti-fuse having a programmed state and an unprogrammed state and coupling the first node to a second power supply when in the programmed state and decoupling the first node from the second power supply when in the unprogrammed state;

a second programming circuit operably connected to the second anti-fuse for selectively changing the second anti-fuse from the unprogrammed state to the programmed state; and

a switch coupled between the second power supply and the first node, wherein the switch includes two transistors.

78. The programmable circuit of claim 77, wherein the switch, when closed, couples the first node to the second power supply regardless of the state of the second anti-fuse, and wherein the switch is responsive to a plurality of input signals.

79. The programmable circuit of claim 77, wherein the second power supply comprises a ground node.

80. The programmable circuit of claim 77, wherein a gate of a first of the two transistors is responsive to an enable signal, and wherein a gate of a second of the two transistors is responsive to a further signal.

81. The programmable circuit of claim 80, wherein the first transistor is connected in parallel with the second transistor.

82. The programmable circuit of claim 81, wherein drains of the first and second transistors are both connected to ground.

83. The programmable circuit of claim 81, wherein the gate of the second transistor is connected to a logic gate that is responsive to a plurality of control signals.

84. The programmable circuit of claim 83, wherein the plurality of control signals include at least one of a fuse bank select signal, a test mode signal, and an address input signal.

85. The programmable circuit of claim 83, wherein the plurality of control signals include a fuse bank select signal, a test mode signal, and an address input signal.

86. A programmable circuit for providing a programmed signal in an integrated circuit, comprising:

a first node, wherein the state of the programmed signal is based on the state of the first node;

a first anti-fuse having a programmed state and an unprogrammed state and coupling the first node to a first power supply when in the programmed state and decoupling the first node from the first power supply when in the unprogrammed state;

a second anti-fuse having a programmed state and an unprogrammed state and coupling the first node to a second power supply when in the programmed state and decoupling the first node from the second power supply when in the unprogrammed state;

a first switch coupled between the second power supply and the first node and responsive to at least one programming control signal, wherein the switch is closed to couple the first node to the second power supply during a programming operation of the integrated circuit regardless of the state of the second anti-fuse and open during normal operation of the integrated circuit;

a second switch coupled between the second power supply and the first node and responsive to an enable signal, wherein the switch is closed to couple the first node to the second power supply based on the enable signal being in a first state regardless of the state of the second anti-fuse, and wherein the switch is open based on the enable signal being in a second state; and

a third switch coupled between the second power supply and the first node and includes two transistors.

87. The programmable circuit of claim 86, wherein the third switch is closed to couple the first node to the second power supply during a programming operation of the integrated circuit and open during normal operations of the integrated circuit.

88. The programmable circuit of claim 86, wherein the first switch and second switch each comprise a transistor.

89. The programmable circuit of claim 86, wherein the second power supply comprises a ground node.

90. The programmable circuit of claim 86, wherein a gate of a first of the two transistors is responsive to an enable signal, and wherein a gate of a second of the two transistors is responsive to a further signal.

91. The programmable circuit of claim 90, wherein the first transistor is connected in parallel with the second transistor.

92. The programmable circuit of claim 91, wherein drains of the first and second transistors are connected to ground.

93. The programmable circuit of claim 90, wherein the gate of the second transistor is connected to a logic gate that is responsive to a plurality of control signals.

94. The programmable circuit of claim 93, wherein the plurality of control signals include at least one of a fuse bank select signal, a test mode signal, and an address input signal.

95. The programmable circuit of claim 93, wherein the plurality of control signals include a fuse bank select signal, a test mode signal, and an address input signal.

96. The programmable circuit of claim 86, wherein the first power supply has a voltage V_cc.

97. A programmable circuit for providing a programmed signal in an integrated circuit, comprising:

a first node, wherein the state of the programmed signal is based on the state of the first node;

a first anti-fuse having a first terminal and a second terminal and having a programmed state and an unprogrammed state, wherein the first terminal is coupled to the first node and couples the first node to the first power supply during normal operation when in the programmed state and decouples the first node from the first power supply when in the unprogrammed state;

a second anti-fuse having a first terminal and a second terminal and having a programmed state and an unprogrammed state, wherein the first terminal is coupled to the first node and couples the first node to the second power supply during normal operation when in the programmed state and decouples the first node from the second power supply when in the unprogrammed state;

a first programming bus carrying a sufficient voltage to short the first anti-fuse;

a first switch coupled to the second terminal of the first anti-fuse for selectively coupling the second terminal of the first anti-fuse to a first power supply during normal operation of the integrated circuit and coupling the second terminal of the first anti-fuse to the first programing bus during a first programming operation of the integrated circuit for programming the first anti-fuse;

a second programming bus carrying a sufficient voltage to short the second anti-fuse;

a second switch coupled to the second terminal of the second anti-fuse for selectively coupling the second terminal of the second anti-fuse to a second power supply during normal operation of the programmable circuit and coupling the second terminal of the second anti-fuse to the second programing bus during a second programming operation of the programmable circuit for programming the second anti-fuse;

wherein only one of the first and second anti-fuses is in the programmed state during normal operation; and

a third switch coupled between the second power supply and the first node and responsive to a plurality of programming control signals, wherein the third switch includes two transistors.

98. The programmable circuit of claim 97, wherein the third switch is closed to couple the first node to the second power supply during a programming operation of the integrated circuit and open during normal operations of the integrated circuit.

99. The programmable circuit according to claim 97, wherein the second power supply is a source of ground potential.

100. The programmable circuit according to claim 97, wherein the first power supply has a voltage V_cc.

101. A programmable circuit for providing a programmed signal in an integrated circuit, comprising:

a first node, wherein the state of the programmed signal is based on the state of the first node;

a first anti-fuse having a programmed state and an unprogrammed state and selectively coupling the first node to a first power supply when in the programmed state and decoupling the first node from the first power supply when in the unprogrammed state;

a second anti-fuse having a programmed state and an unprogrammed state and selectively coupling the first node to a second power supply when in the programmed state and decoupling the first node from the second power supply when in the unprogrammed state;

a first switch coupled between the second power supply and the first node and responsive to at least one programming control signal, wherein the switch is closed to couple the first node to the second power supply during a programming operation of the integrated circuit regardless of the state of the second anti-fuse and open during normal operation of the integrated circuit;

a second switch coupled between the second power supply and the first node and responsive to an enable signal, wherein the switch is closed to couple the first node to the second power supply based on the enable signal being in a first state regardless of the state of the second anti-fuse, and wherein the switch is open based on the enable signal being in a second state;

wherein the only one of the first and second anti-fuses is put in the programmed state at the same time; and

a third switch coupled between the second power supply and the first node and includes two transistors.

102. The programmable circuit of claim 101, wherein the third switch is responsive to a plurality of programming control signals, and wherein the third switch is closed to couple the first node to the second power supply during a programming operation of the integrated circuit and open during normal operations of the integrated circuit.

103. The programmable circuit according to claim 102, wherein the second power supply is a source of ground potential.

104. The programmable circuit according to claim 102, wherein the first power supply has a voltage V_cc.