High speed closed loop amplifier with gain adjustment

• US 6,462,615 B1
• Filed: 10/01/2001
• Issued: 10/08/2002
• Est. Priority Date: 10/01/2001
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Tanghe, Steven John
• Primary Examiner(s): Wells, Kenneth B.
• Application Number:
  US09/682,639
• Time in Patent Office: 372 Days
• Field of Search: 327/108-112, 327/560-563, 330/254, 330/260, 330/261, 330/271, 330/278-285
• US Class Current: 327/560
• CPC Class Codes: H03F 3/45475 using IC blocks as the active amplifying circuit
• CPC Class Codes: H03G 1/0088 using discontinuously variable devices, e.g. switch-operated

Abstract

A method and structure for an integrated circuit including a differential amplifier having at least two inputs and at least two outputs; a pair of first resistors, each of which is coupled to one of the inputs; a pair of first source followers, each of which is coupled to one of the first resistors; a pair of second source followers, each of which is coupled to one of the out puts; a pair of second resistors, each of which is coupled to one of the second source followers and to one of said inputs; and a gain device connected between the first resistors and the first source followers.

Claims

1. An integrated circuit comprising:

a differential amplifier having at least two inputs and at least two outputs;

a pair of first resistors, each of which is coupled to one of said inputs;

a pair of first source followers, each of which is coupled to one of said first resistors;

a pair of second source followers, each of which is coupled to one of said outputs;

a pair of second resistors, each of which is coupled to one of said second source followers and to one of said inputs; and

a gain device connected between said first resistors and said first source followers.

2. The integrated circuit in claim 1, wherein said second source followers and said second resistors make up a feedback loop for said differential amplifier.

3. The integrated circuit chip in claim 1, wherein said gain device controls a gain of said integrated circuit chip without making said integrated circuit sensitive to manufacturing process variations and temperature changes.

4. The integrated circuit in claim 1, wherein said gain device comprises a field effect transistor switching block.

5. The integrated circuit in claim 4, wherein said field effect transistor switching block includes binary weighted resistive switches.

6. The integrated circuit in claim 1, wherein said first source followers are scaled with respect to said second resistors second source followers and in a relationship related to the scaling of said second resistors to said first resistors.

7. The integrated circuit chip in claim 1, further comprising a pair of third source followers, each of which is connected to one of said outputs and to one of said second source followers.

8. An integrated circuit comprising:

a differential amplifier having at least two inputs and at least two outputs;

a pair of first resistors, each of which is coupled to one of said inputs;

a pair of first source followers, each of which is coupled to one of said first resistors;

a pair of second source followers, each of which is coupled to one of said outputs;

a pair of second resistors, each of which is coupled to one of said second source followers and to one of said inputs; and

a resistive field effect transistor switching block operatively connected to said inputs.

9. The integrated circuit in claim 8, wherein said second source followers and said second resistors make up a feedback loop for said differential amplifier.

10. The integrated circuit chip in claim 8, wherein said resistive field effect transistor switching block controls a gain of said integrated circuit chip without making said integrated circuit sensitive to manufacturing process variations and temperature changes.

11. The integrated circuit in claim 8, wherein said resistive field effect transistor switching block includes binary weighted resistive switches.

12. The integrated circuit in claim 8, wherein said first source followers are scaled with respect to said second source followers and in a relationship related to the scaling of said second resistors to said first resistors.

13. The integrated circuit chip in claim 8, further comprising a pair of third source followers, each of which is connected to one of said outputs and to one of said second source followers.

14. An integrated circuit comprising:

a differential amplifier having at least two inputs and at least two outputs;

a first pair of source followers each being coupled to one of the inputs;

a pair of resistors, each of which is coupled to one of the source followers and to one of the inputs;

a gain device operatively connected to the inputs; and

a second pair of source followers connected to the gain device, the second pair of source followers being scaled with respect to the first source followers and in a relationship to the resistors.

15. The integrated circuit of claim 14 further comprising:

a third pair of source followers each coupled to one of the outputs and to one of the second pair of source followers.

16. An integrated circuit comprising:

a differential amplifier having at least two inputs and at least two outputs;

a first pair of some followers each being coupled to one of the inputs; and

a second pair of source followers each being coupled to one of the inputs.

17. The integrated circuit of claim 16 further comprising:

a gain device operatively coupled to each one of the inputs and each one of the second pair of source followers.