Integrated memory having memory cells with magnetoresistive storage effect

• US 6,462,979 B2
• Filed: 03/05/2001
• Issued: 10/08/2002
• Est. Priority Date: 03/03/2000
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Thewes, Roland, Schlösser, Till
• Primary Examiner(s): Hoang, Huan
• Application Number:
  US09/799,626
• Publication Number:
  US 20010026469A1
• Time in Patent Office: 582 Days
• Field of Search: 365/158, 365/157
• US Class Current: 365/158
• CPC Class Codes: G11C 11/15 using multiple magnetic layers G11C11/155 takes precedence
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods

Abstract

The integrated memory has memory cells with a magnetoresistive storage effect in a memory cell array in the form of a matrix. The memory cells are each connected between one of the column lines and one of the row lines. The column lines are each connected to a read amplifier for reading a data signal from a memory cell. The read amplifier has an operational amplifier with feedback, and a first control input connected to one of the column lines. A capacitor is connected between a second control input of the operational amplifier and a terminal for a supply potential and is used to compensate for any offset voltage at the control inputs of the operational amplifier. This allows a data signal which is to be read from one of the memory cells to be detected comparatively reliably.

Claims

1. An integrated memory, comprising:

a memory cell array in form of a matrix having column lines and row lines;

a plurality of memory cells with a magnetoresistive storage effect each connected between one of said column lines and one of said row lines;

read amplifiers respectively connected to each said column line for reading a data signal from a corresponding said memory cell;

said read amplifier having an operational amplifier with a feedback path, and outputting a read signal, said operational amplifier having a first control input connected to one of said column lines and a second control input; and

a capacitor connected between said second control input of said operational amplifier and a supply potential.

2. The integrated memory according to claim 1, which further comprises:

a first switch connected between said first control input and

a terminal for the supply potential;

a second switch connected in said feedback path of said operational amplifier; and

a third switch connected between an output of said operational amplifier and said second control input.

3. The integrated memory according to claim 2, wherein said operational amplifier is an inverting amplifier, and an inversion circuit is connected between said output and said second control input of said operational amplifier.

4. The integrated memory according to claim 1, which comprises a resistor connected in said feedback path of said operational amplifier.

5. The integrated memory according to claim 1, which comprises a further capacitor connected in said feedback path of said operational amplifier.

6. The integrated memory according to claim 5, which comprises a switch connected in parallel with said further capacitor in said feedback path of said operational amplifier.