Post erase repair to enhance performance in a flash memory

• US 6,462,990 B1
• Filed: 12/29/2000
• Issued: 10/08/2002
• Est. Priority Date: 12/29/2000
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Keeney, Stephen N.
• Primary Examiner(s): ZARABIAN, AMIR
• Application Number:
  US09/752,197
• Time in Patent Office: 648 Days
• Field of Search: 365/185.3, 365/185.22, 365/185.24, 365/185.14, 365/185.29
• US Class Current: 365/185.29
• CPC Class Codes: G11C 16/3404 Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
• CPC Class Codes: G11C 16/3409 Circuits or methods to recover overerased nonvolatile memory cells detected during erase verification, usually by means of a "soft" programming step

Abstract

A technique of performing post erase repair on a flash memory by identifying a leaky column after the flash memory is erased. The leaky column is repaired first by programming memory cells of the column to increase the threshold voltage Vt of the memory cells to remove the leaky column condition prior to performing post erase repair on the memory cells. Then, each memory cell is verified and repaired to ensure that each memory cell has a Vt above an acceptable post erase repair value. By performing the column leakage repair first, over erased leakage from deselected cells are not present to give false indications when each cell is verified for the post erase repair Vt.

Claims

1. A method comprising:

identifying a leaky current condition on an output line of a memory after the memory is erased, wherein the memory includes a plurality of memory cells;

increasing a threshold voltage Vt of all memory cells coupled to the output line to remove the leaky current condition on the output line; and

verifying each memory cell coupled to the output line to ensure that each memory cell has a Vt above an acceptable post erase repair value, after the leaky current condition on the output line has been removed.

2. The method of claim 1 in which the verifying includes programming a particular memory cell to increase its Vt, if the particular cell has a Vt below the acceptable post erase repair value.

3. The method of claim 1 in which the verifying includes programming a particular memory cell, if the particular memory cell has a Vt below the acceptable post erase repair value, and wherein the programming is performed until the particular memory cell has its Vt raised above the acceptable post erase repair value.

4. The method of claim 1 in which the memory is a flash memory wherein the memory cells are deselected when identifying the leaky current condition, but are selected for verifying.

5. A method comprising:

identifying a leaky column of memory cells of a flash memory after the flash memory is erased, in which the leaky column exhibits an over erased condition having excessive leakage current;

increasing a threshold voltage Vt of all the memory cells of the leaky column to remove the excessive leakage current; and

verifying each memory cell of the leaky column to ensure that each memory cell has a Vt above an acceptable post erase repair value, after the excessive leakage current on the output line has been removed.

6. The method of claim 5 in which the verifying includes repairing a particular memory cell to increase its Vt, if the particular cell has a Vt below the acceptable post erase repair value.

7. The method of claim 5 in which the verifying includes repairing a particular memory cell, if the particular memory cell has a Vt below the acceptable post erase repair value, and wherein the repairing is performed by programming the particular memory cell until the particular memory cell has its Vt raised above the acceptable post erase repair value.

8. The method of claim 7 in which the programming of the particular memory cell is achieved by incrementally driving a gate voltage of the particular memory cell.

9. A method comprising:

determining if a particular column of memory cells of a flash memory has excessive leakage current on a bitline coupled to the column of memory cells, wherein each memory cell includes a wordline that is deselected;

increasing a threshold voltage Vt of all the memory cells of the column to remove the excessive leakage current, if the column has excessive leakage current, prior to verifying that each memory cell of the column has a Vt above an acceptable post erase value; and

verifying each memory cell of the column by selecting each memory cell individually to ensure that each selected memory cell has a Vt above an acceptable post erase repair value, and if not, repairing the selected memory cell not meeting the post erase repair value by programming the selected memory cell until the Vt is above the acceptable post erase repair value.

10. The method of claim 9 in which the programming to repair the selected memory cell is achieved by increasing its Vt above the acceptable post erase repair value, if the selected memory cell has a Vt below the acceptable post erase repair value.

11. The method of claim 10 in which the programming to repair the selected memory cell is achieved by driving a gate voltage of the selected memory cell.

12. The method of claim 10 in which the programming to repair the selected memory cell is achieved by incrementally driving a gate voltage of the selected memory cell.

13. A machine-readable medium that provides instructions, which when executed by a machine, causes the machine to perform operations comprising:

determining if a particular column of memory cells of a flash memory has excessive leakage current on a bitline coupled to the column of memory cells, wherein each memory cell includes a wordline that is deselected;

increasing a threshold voltage Vt of all the memory cells of the column to remove the excessive leakage current, if the column has excessive leakage current, prior to verifying that each memory cell of the column has a Vt above an acceptable post erase value; and

verifying each memory cell of the column by selecting each memory cell individually to ensure that each selected memory cell has a Vt above an acceptable post erase repair value, and if not, repairing the selected memory cell not meeting the post erase repair value by programming the selected memory cell until the Vt is above the acceptable post erase repair value.

14. The machine-readable medium of claim 13 in which the programming to repair the selected memory cell is achieved by increasing its Vt above the acceptable post erase repair value, if the selected memory cell has a Vt below the acceptable post erase repair value.

15. The machine-readable medium of claim 14 in which the programming to repair the selected memory cell is achieved by driving a gate voltage of the selected memory cell.

16. The machine-readable medium of claim 14 in which the programming to repair the selected memory cell is achieved by incrementally driving a gate voltage of the selected memory cell.