Semiconductor memory device capable of recovering defective bit and a system having the same semiconductor memory device

• US 6,462,995 B2
• Filed: 10/12/2001
• Issued: 10/08/2002
• Est. Priority Date: 03/11/1999
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Urakawa, Yukihiro
• Primary Examiner(s): PHAN, TRONG Q
• Application Number:
  US09/975,149
• Publication Number:
  US 20020015341A1
• Time in Patent Office: 361 Days
• Field of Search: 365/200, 365/225.7
• US Class Current: 365/200
• CPC Class Codes: G11C 29/812 using a reduced amount of fuses

Abstract

The present invention provides a semiconductor memory device capable of simplifying a test process for a memory circuit containing a nonvolatile memory while reducing an overhead of its chip area and a system incorporating the same semiconductor memory device. This semiconductor memory device comprises a proper memory cell array, a redundant memory cell with which the defective memory cell in the proper memory cell array is to be replaced, a register for holding defect information of the defective memory cell detected in the proper memory cell array temporarily; a control circuit for replacing the defective memory cell with the redundant memory cell according to the defect information of the memory cell held in the register, a redundant program array which is an expansion of the same memory cell as the proper memory cell array while sharing a column with the proper memory cell array so as to store defect information in the same column as the defective memory cell, a writing circuit for writing defect information held in the register into the redundant program array, and a reading circuit for reading the defect information stored in the redundant program array into the register.

Claims

1. A semiconductor memory device, comprising:

a) a semiconductor substrate;

b) a semiconductor memory region disposed in said semiconductor substrate and including;

1) a plurality of semiconductor memory elements; and

2) a redundant semiconductor memory element with which a defective memory element in the semiconductor memory elements is to be replaced;

c) a fuse region containing a plurality of fuses configured to store redundancy information according to an address of the defective memory element into or from which data is unable to be written or read;

d) a register circuit connected to said fuse region, said register circuit being configured to receive and hold said redundancy information stored in said fuse region based on whether or not a fuse provided in said fuse region is cut and to transmit said redundancy information; and

e) a transfer circuit configured to transfer said redundancy information received from said register circuit to said semiconductor memory region serially so that the defective semiconductor memory element is replaced with the redundant semiconductor memory element;

wherein each of said fuse region, said register circuit and said transfer circuit is disposed in an end portion or said semiconductor substrate.

2. The semiconductor memory device according to claim 1, wherein said fuse region concentrates in a single portion in said semiconductor substrate.

3. The semiconductor memory device according to claim 2, wherein said register circuit and said transfer circuit concentrate in a single portion in said semiconductor substrate.

4. The semiconductor memory device according to claim 1, wherein said register circuit and said transfer circuit concentrate in a single portion in said semiconductor substrate.

5. The semiconductor memory device according to claim 1, further comprising:

a single signal wire configured to connect said transfer circuit and said semiconductor memory region.

6. The semiconductor memory device according to claim 1, further comprising:

a plurality of pads disposed along neighborhood of the end portion of semiconductor substrate, said end portion having said fuse region, said register circuit and said transfer circuit.

7. The semiconductor memory device according to claim 1, wherein said transfer circuit is substantially disposed in a center portion of one side in said semiconductor substrate.

8. The semiconductor memory device according to claim 1, wherein both of said register circuit and said transfer circuit is disposed along one side in said semiconductor substrate.

9. The semiconductor memory device according to claim 1, wherein said transfer circuit is disposed substantially in a line with said plurality of pads disposed along neighborhood of the end portion of said semiconductor substrate.

10. The semiconductor memory device according to claim 1, wherein said semiconductor memory region includes a volatile memory.

11. The semiconductor memory device according to claim 1, wherein said fuse region is provided in a pad formation region out of said semiconductor memory region.

12. The semiconductor memory device according to claim 1, wherein said register circuit is provided in a pad formation region out of said semiconductor memory region.

13. The semiconductor memory device according to claim 1, wherein a number of fuses contained in said fuse region corresponds to a number of columns of the memory elements.

14. The semiconductor memory device according to claim 1, wherein:

said register circuit electrically forms a determination whether or not said fuse is cut, and

said redundancy information held by said register circuit is updated in accordance with the determination formed by said register circuit.

15. A system incorporating a semiconductor memory device, comprising:

a) a semiconductor substrate;

b) a semiconductor memory region disposed in said semiconductor substrate and including;

1) a plurality of semiconductor memory elements; and

2) a redundant semiconductor memory element with which a defective memory element in the semiconductor memory elements is to be replaced;

c) a fuse region configured to store redundancy information according to an address of the defective memory elements into or from which data is unable to be written or read;

d) a register circuit connected to said fuse region, said register circuit being configured to receive and hold said redundancy information stored in said fuse region based on whether or not a fuse provided in said fuse region is cut and to transmit said redundancy information;

e) a transfer circuit configured to transfer said redundancy information received from said register circuit to said semiconductor memory region serially so that the defective semiconductor memory element is replaced with the redundant semiconductor memory element;

f) a control circuit for replacing the defective memory element with the redundant memory element according to the redundancy information of the memory element held in said register circuit; and

g) a processing unit for carrying out a desired processing using the semiconductor memory device;

wherein each of said fuse region, said register circuit and said transfer circuit is disposed in an end portion of said semiconductor substrate.

16. The system according to claim 15, wherein the control circuit includes a built-in self-repair circuit.

17. The system according to claim 15, wherein said fuse region concentrates in a single portion in said semiconductor substrate.

18. The system according to claim 15, wherein said register circuit and said transfer circuit concentrate in a single portion in said semiconductor substrate.

19. The system according to claim 15, further comprising:

a single signal wire configured to connect said transfer circuit and said semiconductor memory region.

20. The system according to claim 15, further comprising:

a plurality of pads disposed along neighborhood of the end portion of semiconductor substrate, said end portion having said fuse region, said register circuit and said transfer circuit.