Network switching system having overflow bypass in internal rules checker

• US 6,463,032 B1
• Filed: 01/27/1999
• Issued: 10/08/2002
• Est. Priority Date: 01/27/1999
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Chiang, John M., Merchant, Shashank C., Lau, Michael Vengchong
• Primary Examiner(s): Kizou, Hassan
• Assistant Examiner(s): Tsegaye, Saba
• Application Number:
  US09/238,047
• Time in Patent Office: 1,350 Days
• Field of Search: 370/229, 370/231, 370/235, 370/216-218, 370/221, 370/412-414, 370/416, 370/418, 370/428, 370/429
• US Class Current: 370/218
• CPC Class Codes: H04L 49/205 Quality of Service based
• CPC Class Codes: H04L 49/3027 Output queuing
• CPC Class Codes: H04L 49/351 for local area network [LAN], e.g. Ethernet switches
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/901 using storage descriptor, e.g. read or write pointers
• CPC Class Codes: H04L 49/9078 using an external memory or storage device

Abstract

A novel method of overflow data handling in a multiport data switching system having a decision making engine for controlling data forwarding between receive ports and at least one transmit port. Data blocks representing received data packets are placed in data queues corresponding to the receive ports. The data queues are transferred to logic circuitry for processing in accordance with a prescribed algorithm. Then, a forwarding decision is made to determine the transmit port. An overflow bypass is provided to allow at least a portion of a data block to bypass the logic circuitry, when at least one of the data queues is in an overflow state. For example, pointers indicating memory locations for storing the corresponding received data packets may be transferred via the overflow bypass when the overflow state is detected.

Claims

1. A multiport data communication system for transferring data packets between ports, the data communication system comprising:

a plurality of receive ports for receiving data packets,

a decision making engine responsive to the received data packets for controlling transmission of the received data packets to at least one selected transmit port,

the decision making engine including;

a plurality of queuing devices corresponding to the plurality of the receive ports for queuing data blocks representing the data packets received by the corresponding receive ports,

logic circuitry responsive to the plurality of queuing devices for processing the data blocks in accordance with a prescribed algorithm,

a forwarding circuit responsive to the logic circuitry for identifying the at least one selected transmit port for each data packet, and

an overflow handling circuit for providing an overflow bypass for bypassing the logic circuitry to transfer at least a portion of a data block representing a received data packet directly to the forwarding circuit when at least one of the plurality of the queuing devices is in an overflow state.

2. The system of claim 1, wherein the data blocks include pointers for indicating memory locations for storing the received data packets.

3. The system of claim 2, wherein the overflow handling circuit is configured to allow the pointers to bypass the logic circuitry.

4. The system of claim 1, wherein the overflow handling circuit comprises a plurality of overflow registers corresponding to the plurality of the receive ports for holding overflow data when the corresponding queuing device is in the overflow state.

5. The system of claim 4, wherein each of the overflow registers comprises first and second sections, each of the sections is configured for storing the at least a portion of a data block.

6. The system of claim 5, wherein the overflow handling circuit is configured to supply the at least a portion of a data block to the first section of an overflow register when the overflow handling circuit detects that the corresponding queuing device is in the overflow state.

7. The system of claim 6, wherein the overflow handling circuit is configured to transfer the at least a portion of a data block from the first section to the second section of the overflow register when an end of a data packet represented by the data block is detected.

8. The system of claim 4, wherein the overflow handling circuit comprises at least one arbitrator for performing arbitration between requests for access to the forwarding circuit for the plurality of overflow registers.

9. The system of claim 8, wherein the plurality of receive ports include regular ports, at least one high-speed port for receiving data packets at a rate higher than a rate at the regular ports, and at least one expansion port for receiving data packets from other communication systems.

10. The system of claim 9, wherein requests for access to the forwarding circuit for the overflow registers corresponding to the high-speed and expansion ports have a higher priority than requests for access to the forwarding circuit for the overflow registers corresponding to the regular ports.

11. The system of claim 9, wherein the overflow handling circuit comprises a first arbitrator for performing arbitration between requests for access to the forwarding circuit for the overflow registers corresponding to the regular ports.

12. The system of claim 10, wherein the overflow handling circuit comprises a second arbitrator for performing arbitration between requests for access to the forwarding circuit for the overflow registers corresponding to the high-speed and expansion ports.

13. The system of claim 8, wherein the at least one arbitrator is responsive to a request for access to the forwarding circuit for an overflow register of the plurality of overflow registers to produce a grant signal for enabling the forwarding circuit to receive the overflow data from the overflow register.

14. In a communication system having a plurality of receive ports, at least one transmit port, and a decision making engine for controlling data forwarding between the receive port and the at least one transmit port, a method of handling data overflow comprising the steps of:

placing data blocks representing received data packets in a plurality of data queues corresponding to the plurality of the receive ports,

processing the data queues by logic circuitry in accordance with a prescribed algorithm,

making a forwarding decision to determine the at least one transmit port, and

providing an overflow bypass to allow at least a portion of a data block representing a received data packet to bypass the logic circuitry, when at least one of the plurality of data queues is in an overflow state.

15. The method of claim 14, wherein the data blocks include pointers for indicating memory locations for storing the received data packets.

16. The method of claim 15, wherein the pointers are allowed to bypass the logic circuitry when the overflow state is detected.

17. The method of claim 14, wherein the step of providing an overflow bypass comprises buffering overflow data in a plurality of overflow registers corresponding to the plurality of receive ports.

18. The method of claim 17, wherein the step of providing an overflow bypass further comprises performing arbitration between requests for transferring the overflow data from the plurality of the overflow registers.

19. The method of claim 17, wherein the overflow data is buffered in a first section of an overflow register when the overflow state is detected.

20. The method of claim 19, wherein the overflow data is transferred from the first section to a second section of the overflow register when an end of a data packet represented by the overflow data is detected.