Signal processing circuit

• US 6,463,060 B1
• Filed: 06/01/2001
• Issued: 10/08/2002
• Est. Priority Date: 04/01/1997
• Status: Expired due to Fees

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Sato, Sadaharu, Aoki, Tetsuya, Muto, Takayasu
• Primary Examiner(s): Olms, Douglas
• Assistant Examiner(s): VANDERPUYE, KENNETH N
• Application Number:
  US09/872,964
• Time in Patent Office: 494 Days
• Field of Search: 370/389, 370/428, 370/503, 370/517, 370/521, 348/425.1, 348/423.1, 348/474, 348/500
• US Class Current: 370/389
• CPC Class Codes: H04J 3/0685 Clock or time synchronisation in a node; Intranode synchronisation
• CPC Class Codes: H04L 12/40058 Isochronous transmission
• CPC Class Codes: H04L 12/40071 Packet processing; Packet format adaptation of digital video signals for transport over a specific network H04N21/2381, H04N21/4363, H04N21/4381; packet switches H04L49/00; intermediate storage or scheduling H04L49/90
• CPC Class Codes: H04L 12/40117 Interconnection of audio or video/imaging devices home automation networks H04L12/2803; bitstream network arrangements specially adapted for distribution of digital video signals H04N7/24
• CPC Class Codes: H04L 69/08 Protocols for interworking; Protocol conversion
• CPC Class Codes: H04L 69/28 Timers or timing mechanisms used in protocols

Abstract

A signal processing circuit which enables an error bit to be set simply without causing an increase in the size of the circuit even if the packet size is changed and which enables realization of stable operation without the system stopping even if the value of the time stamp is impossible. A pre-reception processing circuit decides if a received packet is normally continuous or discontinuous from data in the DBC region of the CIP header. When deciding it is discontinuous, it sets an error bit ERM allocated to one bit of the upper significant 7 bits of the source packet header to “1”, and writes this in an FIFO. A post-reception processing circuit, when reading from the FIFO, outputs the data stored in the FIFO to the application side when the error bit ERM is “0” and resets the error bit and outputs a dummy error packet when the error bit EMR is “1”.

Claims

1. A signal processing circuit for receiving packet data transmitted through a serial interface bus in a predetermined time cycle and outputting the packet data to an application side, comprising:

a memory means;

a first reception circuit for receiving transmitted packets, deciding whether every received packet is transmitted according to a predetermined serial data bus standard, adding an error mark to a packet when it is determined that the packet was not transmitted according to the standard, and storing the packet with error mark added thereto in the memory means, and

a second reception circuit for performing a process in accordance with the error and outputting the result of the process to the application side when said error mark is added to packet data.

2. A signal processing circuit according to claim 1, wherein

the packets transmitted over the serial bus have control information indicating whether the transmitted packets are continuous or not,

the first reception circuit adds the error mark to the respective received packets when deciding from the control information that the received packets are not continuous, and

the second reception circuit outputs an error packet to the application side in place of the packet data with the error mark stored in the memory means when an error mark is added.

3. A signal processing circuit according to claim 1, wherein

each of the source packets transmitted over the serial bus has a source packet header containing time information set with a time for the reception side to output the received data to the application side,

the first reception circuit adds the error mark when the time information indicates a time exceeding a predetermined time, and

the second reception circuit outputs the packet data stored in the memory means regardless of whether or not an error mark associated with the time information has been added.

4. A signal processing circuit according to claim 3, further comprising:

a counting means for counting time, and

the second reception circuit fetches the time information of the source packet header stored in the memory means when an error mark is not added and outputs the received data to the application side when the value of the time counted by the counting means is larger than the value of the time information.

5. A signal processing circuit according to claim 1, wherein the error mark is added to the packet by setting a bit at a specific position within a header of the received packet to a predetermined value.

6. A signal processing circuit according to claim 1, wherein said process in accordance with the error comprises generating a dummy packet when the error mark is added, said dummy packet being output to the application side.

7. A signal processing circuit for adding time information to packet data and transmitting the packet data with the time information added thereto over a serial interface bus in a predetermined time cycle, said time information designating a time during which a reception side is to output received data to an application side, said signal processing circuit comprising:

a counting means for counting time,

a control means to set a delay time to be added according to the amount of transmission data,

a memory means,

a first transmission circuit for setting the time information based on the delay time set by the control means, adding the set time information to transmission data and storing the transmission data with the time information added thereto in the memory means, and

a second transmission circuit for setting a threshold according to the amount of transmission data, deciding whether the set time information is valid or not from the set threshold, the delay time and the time counted by the counting means, reading the packet data having the time information and transmitting it as the transmission data when valid, and skipping the packet and processing the next packet when it is invalid.

8. A signal processing circuit according to claim 7, wherein when a current time indicated by the counting means is less than the set time information, the second transmission circuit decides the transmission is valid when the value of the time information minus the current time is smaller than a maximum value of the delay time and larger than the threshold set according to the amount of data and decides the transmission is invalid when at least one of a condition that the value of the time information minus the current time is larger than the maximum value of the delay time or smaller than the threshold set according to the amount of data is satisfied.

9. A signal processing circuit according to claim 7, wherein when a current time indicated by the counting means is larger than the set time information, the second transmission circuit decides the transmission is valid when the current time minus the value of the time information is larger than the maximum count width value of a cycle count of the time information minus the maximum value of the delay time and is less than the maximum count width value minus the above threshold and decides the transmission is invalid when at least one of a condition that the current time minus the time information is smaller than the maximum count width value of the cycle count of the time information minus the maximum value of the delay time or is larger than the maximum count width value minus the threshold is satisfied.

10. A signal processing circuit according to claim 8, wherein when the current time indicated by the counting means is larger than the set time information, the second transmission circuit decides the transmission is valid when the current time minus the time information is larger than the maximum count width value of a cycle count of the time information minus the maximum value of the delay time and is less than the maximum count width value minus the threshold and decides the transmission is invalid when at least one of a condition that the current time minus the time information is less than the maximum count width value of the cycle count of the time information minus the maximum value of the delay time or larger than the maximum count width value minus the threshold is satisfied.

11. A signal processing circuit according to claim 7, wherein the second transmission circuit sets the threshold according to fractions of the unit packets transmitted.

12. A signal processing circuit according to claim 7, wherein the counting means counts the predetermined cycle time for every packet to be transmitted.

13. A signal processing circuit for receiving packet data having time information set with a time for a reception side to output the received data to an application side and transmitted over a serial interface bus in a predetermined time cycle and outputting the result to the application side, comprising:

counting means for counting time and

reception means for reading the time information from the received packet data and outputting the received data to the application side when the time counted by the counting means exceeds the value of the time information;

wherein the reception means comprises;

a memory means;

pre-processing means for restoring data from the received packet data, storing the restored data in the memory means with the time information, and outputting an information signal indicating that the restored data has been stored in the memory means,

comparison means for receiving the information signal of the preprocessing means, reading the time information stored in the memory means, comparing the time information and the time counted by the counting means, and outputting a data read instruction signal when the count is larger, and

data read control means for reading the data stored in the memory means and outputting the same to the application side if the data read instruction signal is received thereby.

14. A signal processing circuit for receiving packet data having time information set with a time for a reception side to output received data to an application side and transmitted over a serial interface bus in a predetermined time cycle and outputting the result to the application side, comprising:

reception means for receiving the packet data from the serial bus; and

means for determining if the time information of the packet data received by the reception means indicates a value exceeding a predetermined valid time value, and if so, outputting the received data to the application side;

wherein said predetermined time value is represented by a code having a first valid value for a predetermined group of most significant bits, and a second valid value for a predefined group of least significant bits; and

said means for determining immediately outputs the received data to the application side if it determines that a corresponding group of most significant bits of the packet data time information has a value exceeding the first valid value for the group of most significant bits of the code, or if a corresponding group of least significant bits of the packet data time information has a value exceeding the second valid value for the group of least significant bits of the code.

15. A signal processing circuit for receiving packet data having time information set with a time for a reception side to output received data to an application side and transmitted over a serial interface bus in a predetermined time cycle and outputting the same to the application side, comprising:

a counting means for counting time; and

reception means for reading the time information from the received packet data and outputting the received data to the application side when the time counted by the counting means exceeds the value of the time information or the time information indicates a time exceeding a predetermined time;

wherein the reception means comprises;

a memory means;

pre-processing means for restoring data from the received packet data, storing the restored data in the memory means with the time information, and outputting an information signal indicating that the restored data has been stored in the memory means,

comparison means for receiving the information signal of the pre-processing means, reading the time information stored in the memory means, comparing the time information and the time counted by the counting means, and outputting a data read instruction signal when the count is larger,

decision means for deciding whether the time information indicates a time exceeding a predetermined time or not and outputting a data read instruction signal when exceeding it, and

data read control means for reading the data stored in the memory means and outputting the result to the application side if receiving the data read instruction signal of the comparison means or the decision means.

16. A signal processing circuit for receiving packet data having time information set with a time for a reception side to output received data to an application side and transmitted over a serial interface bus in a predetermined time cycle and outputting the result to the application side, comprising:

receiving means for receiving the packet data from the serial interface bus;

means for indicating a time stamp disable condition; and

control means for outputting the packet data received by the receiving means to the application side regardless of the value of the time information of the received packet data, when the time stamp disable condition is indicated.

17. A signal processing circuit for receiving packet data having time information set with a time for a reception side to output received data to an application side and transmitted over a serial interface bus in a predetermined time cycle and outputting the result to the application side, comprising:

a counting means for counting time,

a reception circuit for reading the time information from the received packet data and outputting the received data to the application side when the value counted by the counting means is larger than the value of the time information,

means for indicating a time stamp disable condition; and

control means for causing the reception circuit to output the received data to the application side regardless of the value of the time information, when the time stamp disable condition is indicated.

18. A signal processing circuit for receiving packet data having time information set with a time for a reception side to output received data to an application side and transmitted over a serial interface bus in a predetermined time cycle and outputting the result to the application side, comprising:

counting means for counting time,

reception means for reading the time information from the received packet data and outputting the received data to the application side when the value counted by the counting means is larger than the value of the time information, and

control means for causing the reception means to output the received data to the application side regardless of the value of the time information,

wherein the reception means comprises;

memory means;

pre-processing means for restoring data from the received packet data, storing the result in the memory means with the time information, and outputting an information signal indicating that the restored data has been stored in the memory means,

comparison means for receiving the stored information signal of the pre-processing circuit, reading the time information stored in the memory means, comparing the time information and the time counted by the counting means, and outputting a data read instruction signal when the count is larger, and

data read control means for reading the data stored in the memory means and outputting it to the application side when receiving the data read instruction signal and receiving the received data stored in the memory means and outputting it to the application side regardless of the time information based on the stored information signal when receiving a control signal from the control means.