Method and apparatus for sharing access to a bus

• US 6,463,072 B1
• Filed: 12/28/1999
• Issued: 10/08/2002
• Est. Priority Date: 12/28/1999
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Bernstein, Debra, Wolrich, Gilbert, Adiletta, Matthew
• Primary Examiner(s): Yao, Kwang Bin
• Assistant Examiner(s): JONES, PRENELL P
• Application Number:
  US09/473,570
• Time in Patent Office: 1,015 Days
• Field of Search: 370/458, 370/438-442, 370/503, 370/327, 422/427, 229/230, 282/352, 390/395, 331/462-468, 331/402-410, 338/474, 338/255, 338/412, 709/248-256, 709/231, 709/321, 709/228-230, 710/22, 710/52, 710/8-10, 710/202, 710/107-113, 710/102, 714/4, 714/33-34, 713/400, 345/522, 712/28
• US Class Current: 370/439
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/901 using storage descriptor, e.g. read or write pointers

Abstract

A router includes a communications bus, a second bus, and at least two processors. The second bus transfers ready status data from ports connected to the communications bus. The processors are connected to the communications and second busses. One of the processors controls the communications bus at each time. Each processor transfers control of the communications bus to another processor in response to receiving a request for control from the other processor.

Claims

1. A router comprising:

a communications bus;

a second bus to transfer ready status data from ports connected to the communications bus; and

at least two processors connected to the communications and second busses, one of the processors to control of the communications bus at any time, each processor to transfer control of the communications bus to another of the processors in response to receiving a request for control from the other of the processors, each port being assignable to a corresponding processor of the processors such that a data packet received at one of the ports is processed by the corresponding processor, the corresponding processor to retransmit the received data packet to another of the ports.

2. The router of claim 1, wherein each processor can transmit and receive a token, one of the processors transmitting the token to a target processor to transfer control of the communications bus to the target processor.

3. The router of claim 2, further comprising:

a plurality of lines; and

wherein each processor has terminals to transmit and receive the token, one of the lines connecting the terminal to transmit the token of one of the processors to the terminal to receive the token of another of the processors.

4. The router of claim 3, wherein each processor further comprises terminals to transmit and receive requests for the token.

5. The router of claim 2, further comprising:

a plurality of devices connected to the communications and second busses, each device capable of transmitting data between an associated network and the communications bus.

6. The router of claim 5, wherein a preselected one of the processors can poll the devices for ready status data.

7. The router of claim 6, wherein the other processor monitors the second bus for ready status data.

8. The router of claim 6, wherein the first and second processors process data packets received from first and second groups of the devices, the first and second groups not having common members.

9. A method of sharing control of a communications bus, comprising:

determining whether a first processor is a master of the communications bus;

requesting that a second processor designate the first processor to be the master of the communications bus in response to the second processor being the master; and

transferring a data packet between the first processor and the communications bus in response to the first processor being designated to be the master.

10. The method of claim 9, further comprising:

transferring a data packet between the first processor and the communications bus in response to determining that the first processor is the master.

11. The method of claim 9, further comprising:

sending a token from the second processor to the first processor in response to the requesting, the sending designating the first processor to be the master.

12. The method of claim 9, wherein the requesting includes driving a request input terminal of the second processor with a preselected voltage associated with a request for the designation of the master.

13. The method of claim 9, further comprising:

determining whether the first processor has scheduled a data transfer over the communications bus, the requesting being responsive to determining that the first processor has a scheduled data transfer.

14. A method of transferring data, comprising:

receiving at a second processor a request from a first processor, the request being for control of a communications bus;

determining whether a second processor is idle in response to receiving the request; and

transferring control from the second processor to the first processor in response to the second processor being idle.

15. The method of claim 14, wherein the second processor is idle if the second processor does not have scheduled data transfers with devices connected to the communications bus.

16. The method of claim 14, wherein the transferring comprises sending a bus-control token from the second processor from the first processor.

17. The method of claim 15, further comprising:

performing one scheduled data transfer from the second processor over the communications bus in response to the receiving the request from the first processor; and

then, transferring the control of the communications bus to the first processor.