Apparatus and method for testing master logic units within a data processing apparatus

• US 6,463,488 B1
• Filed: 06/14/1999
• Issued: 10/08/2002
• Est. Priority Date: 06/22/1998
• Status: Expired due to Fees

• Current Assignee: Arm Limited (SoftBank Group Corp.)
• Original Assignee: Arm Limited (SoftBank Group Corp.)
• Inventors: San Juan, Martin
• Primary Examiner(s): MYERS, PAUL R
• Application Number:
  US09/332,526
• Time in Patent Office: 1,212 Days
• Field of Search: 710/107, 710/113-125, 710/240-244, 714/10, 714/11, 714/23
• US Class Current: 710/107
• CPC Class Codes: G06F 11/2221 to test input/output devices or peripheral units
• CPC Class Codes: G06F 11/2242 in multi-processor systems, e.g. one processor becoming the test master G06F11/2736 takes precedence
• CPC Class Codes: G06F 13/364 using independent requests or grants, e.g. using separated request and grant lines

Abstract

The present invention provides a data processing apparatus and method of testing a master logic unit within a data processing apparatus, the data processing apparatus comprising one or more master logic units for accessing a bus in order to initiate processing requests, and a test controller for testing logic units of the data processing apparatus. Further, an arbiter is provided for receiving bus request signals from the test controller and the one or more master logic units, and for applying predetermined priority criteria to control access to the bus by the test controller and the master logic units, the predetermined priority criteria identifying the relative priority of each master logic unit and the test controller. In a normal test mode, the test controller has a higher priority than any of the master logic units to be tested. However, in a master test mode, when master functionality of a first master logic unit is to be tested by the test controller, the arbiter is arranged to receive a priority access signal to cause the arbiter to assign the first master logic unit a higher priority than the test controller, in order to allow the first master logic unit to have access to the bus in order to generate a test processing request.

By this approach, the master logic unit being tested can fully exercise its master functionality, since the master logic unit is allowed to drive processing requests onto the bus in a controlled manner.

Claims

1. A data processing apparatus, comprising:

one or more master logic units for accessing a bus in order to generate processing requests;

a test controller for testing said master logic units of the data processing apparatus;

an arbiter for receiving bus request signals from the test controller and the one or more master logic units, and for applying predetermined priority criteria to control access to the bus by the test controller and the master logic units, the predetermined priority criteria identifying the relative priority of each master logic unit and the test controller;

in a normal test mode, the test controller having a higher priority than any of the master logic units to be tested; and

in a master test mode, when master functionality of a first master logic unit is to be tested by the test controller, the arbiter being arranged to receive a priority access signal to cause the arbiter to assign the first master logic unit a higher priority than the test controller, in order to allow the first master logic unit to have access to the bus in order to generate a test processing request.

2. A data processing apparatus as claimed in claim 1, wherein upon completion of the test processing request, the priority access signal is deactivated, so that subsequent access to the bus is controlled by the predetermined priority criteria.

3. A data processing apparatus as claimed in claim 1, wherein upon completion of the test processing request, the test controller is arranged to access the results of the test processing request performed by the first master logic unit.

4. A data processing apparatus as claimed in claim 1, wherein the priority access signal comprises a priority enable signal arranged to cause the arbiter to assign the first master logic unit a higher priority than the test controller, such that the first master logic unit will be given access to the bus upon issuing its normal bus request signal.

5. A data processing apparatus as claimed in claim 1, wherein the first master logic unit comprises test logic for controlling testing of the first master logic unit in said normal test mode.

6. A data processing apparatus, comprising:

one or more master logic units for accessing a bus in order to generate processing requests;

a test controller for testing said master logic units of the data processing apparatus;

an arbiter for receiving bus request signals from the test controller and the one or more master logic units, and for applying predetermined priority criteria to control access to the bus by the test controller and the master logic units, the predetermined priority criteria identifying the relative priority of each master logic unit and the test controller;

in a normal test mode, the test controller having a higher priority than any of the master logic units to be tested; and

in a master test mode, when master functionality of a first master logic unit is to be tested by the test controller, the arbiter being arranged to receive a priority access signal to cause the arbiter to assign the first master logic unit a higher priority than the test controller, in order to allow the first master logic unit to have access to the bus in order to generate a test processing request, wherein the priority access signal comprises a priority enable signal arranged to cause the arbiter to assign the first master logic unit a higher priority than the test controller, such that the first master logic unit will be given access to the bus upon issuing its normal bus request signal, wherein the master logic unit is arranged to assert its normal bus request signal to request access to the bus in order to enable the test processing request to be driven onto the bus, and the arbiter is arranged to grant the first master logic unit access to the system bus if the priority enable signal is asserted.

7. A data processing request as claimed in claim 6, wherein the master logic unit is arranged to disassert its normal bus request signal upon completion of the test processing request, thereby allowing the test controller to be granted access to the bus.

8. A data processing apparatus comprising:

one or more master logic units for accessing a bus in order to generate processing requests;

a test controller for testing said master logic units of the data processing apparatus;

an arbiter for receiving bus request signals from the test controller and the one or more master logic units, and for applying predetermined priority criteria to control access to the bus by the test controller and the master logic units, the predetermined priority criteria identifying the relative priority of each master logic unit and the test controller;

in a normal test mode, the test controller having a higher priority than any of the master logic units to be tested; and

in a master test mode, when master functionality of a first master logic unit is to be tested by the test controller, the arbiter being arranged to receive a priority access signal to cause the arbiter to assign the first master logic unit a higher priority than the test controller, in order to allow the first master logic unit to have access to the bus in order to generate a test processing request, wherein the first master logic unit contains a test register from which the priority access signal is asserted, and the priority access signal is asserted to the arbiter by the first master logic unit when the first master logic unit is to be tested in said master test mode.

9. A data processing apparatus as claimed in claim 8, wherein upon initiating a test of the first master logic unit in said master test mode, the test controller is arranged to cause the priority access signal to be asserted via the test register of the first master logic unit.

10. A data processing apparatus as claimed in claim 9, wherein the test controller is arranged to write a first logic value into the test register to cause the priority access signal to be asserted.

11. A data processing apparatus as claimed in claim 10, wherein upon being granted access to the bus after completion of the test processing request by the first master logic unit, the test controller is arranged to write a second logic value into the test register of the first master logic unit to cause the priority access signal to be disasserted.

12. A data processing apparatus comprising:

one or more master logic units for accessing a bus in order to generate processing requests;

a test controller for testing said master logic units of the data processing apparatus;

an arbiter for receiving bus request signals from the test controller and the one or more master logic units, and for applying predetermined priority criteria to control access to the bus by the test controller and the master logic units, the predetermined priority criteria identifying the relative priority of each master logic unit and the test controller;

in a normal test mode, the test controller having a higher priority than any of the master logic units to be tested; and

in a master test mode, when master functionality of a first master logic unit is to be tested by the test controller, the arbiter being arranged to receive a priority access signal to cause the arbiter to assign the first master logic unit a higher priority than the test controller, in order to allow the first master logic unit to have access to the bus in order to generate a test processing request, wherein;

the arbiter comprises a priority encoder for receiving the priority access signal and any bus request signals from the test controller and the one or more master logic units;

the arbiter being arranged to apply the predetermined priority criteria in the absence of said priority access signal in order to generate a signal identifying which of the test controller and master logic units requesting the bus has the highest priority; and

the arbiter being arranged upon receipt of the priority access signal to assign the first master logic unit a higher priority than the test controller irrespective of the predetermined priority criteria and to generate a signal identifying the highest priority master logic unit requesting the bus.

13. A data processing apparatus as claimed in claim 12, wherein the arbiter further comprises grant generation logic for receiving the signal from the priority encoder, and for sending a bus grant signal to the test controller or one of the master logic units, as identified by the signal from the priority encoder.

14. A method of testing a master logic unit within a data processing apparatus, the data processing apparatus comprising one or more master logic units arranged to access a bus in order to generate processing requests, a test controller for testing logic units of the data processing apparatus, and an arbiter for receiving bus request signals from the test controller and the one or more master logic units, and for applying predetermined priority criteria to control access to the bus by the test controller and the master logic units, the predetermined priority criteria identifying the relative priority of each master logic unit and the test controller, the method comprising the steps of:

(a) arranging the test controller to initiate a test of master functionality of the first master logic unit in a master test mode;

(b) issuing a priority access signal to bit to cause the arbiter to assign the first master logic unit a higher priority than the test controller;

(c) granting the first master logic unit access to the system bus; and

(d) arranging the first master logic unit to generate a test processing request.

15. A method as claimed in claim 14, wherein the priority access signal comprises a priority enable signal arranged to cause the arbiter to assign the first master logic unit a higher priority than the test controller, and said step (c) comprises granting the first master logic unit access to the bus when the first master logic unit issues its normal bus request signal.

16. A method as claimed in claim 15, wherein the master logic unit is arranged to assert its normal bus request signal to request access to the bus in order to enable the test processing request to be driven onto the bus, and the first master logic unit is granted access to the system bus at said step (c) if the priority enable signal is asserted.

17. A method as claimed in claim 16, wherein the master logic unit is arranged to disassert its normal bus request signal upon completion of the test processing request, thereby allowing the test controller to be granted access to the bus.

18. A method of testing a master logic unit within a data processing apparatus, the data processing apparatus comprising one or more master logic units arranged to access a bus in order to generate processing requests, a test controller for testing logic units of the data processing apparatus, and an arbiter for receiving bus request signals from the test controller and the one or more master logic units, and for applying predetermined priority criteria to control access to the bus by the test controller and the master logic units, the predetermined priority criteria identifying the relative priority of each master logic unit and the test controller, the method comprising the steps of:

(a) arranging the test controller to initiate a test of master functionality of the first master logic unit in a master test mode;

(b) issuing a priority access signal to the arbiter to cause the arbiter to assign the first master logic unit a higher priority than the test controller;

(c) granting the first master logic unit access to the system bus; and

(d) arranging the first master logic unit to generate a test processing request,

wherein said step (b) comprises the step of the first master logic unit asserting the priority access signal to the arbiter when the first master logic unit is to be tested in said master test mode.

19. A method as claimed in claim 18, wherein upon initiating a test of the first master logic unit in said master test mode at said step (a), the test controller is arranged to cause the priority access signal to be asserted by the first master logic unit at said step (b).