Dual on-chip and in-package clock distribution system
First Claim
1. A clock distribution system for a packaged semiconductor device, comprising:
- an on-chip clock distribution network for transmitting a clock signal between a clock source and clocked logic;
an in-package clock distribution network for transmitting the clock signal between the clock source and the clocked logic; and
a mode selector for providing the clock signal supplied by either the on-chip clock distribution network or the in-package clock distribution network to the clocked logic.
5 Assignments
0 Petitions
Accused Products
Abstract
A clock distribution system for a semiconductor device provides for both on-chip and in-package clock distribution via on-chip and in-package clock distribution networks. Each of these networks is selectively enabled depending on the mode of operation. Specifically, for wafer testing, the on-chip clock distribution network is selected. Thus, a probe tester need only provide a single clock source with conventional timing specifications to test the operation of the chip. In contrast, during normal operation, an in-package clock distribution network is enabled. In-package clock routing provides the lowest variation mode and thus, will result in the maximum clock frequency for the chip.
28 Citations
19 Claims
-
1. A clock distribution system for a packaged semiconductor device, comprising:
-
an on-chip clock distribution network for transmitting a clock signal between a clock source and clocked logic;
an in-package clock distribution network for transmitting the clock signal between the clock source and the clocked logic; and
a mode selector for providing the clock signal supplied by either the on-chip clock distribution network or the in-package clock distribution network to the clocked logic. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
a clock source demultiplexer, which is located near the clock source for the chip, for providing the clock signal on either the on-chip clock distribution network or the in-package clock distribution network; and
a logic multiplexer, which is located near the clocked logic on the chip, for providing the clock signal from either the on-chip clock distribution network or the in-package clock distribution network to control the clocked logic.
-
-
11. A clock distribution system as claimed in claim 1, wherein the mode selector disables the in-package distribution network during testing of the packaged semiconductor device.
-
12. A clock distribution method for a packaged semiconductor device, the method comprising:
-
providing for the distribution of a clock signal via an on-chip clock distribution network from a clock source to clocked logic during testing; and
distributing a clock signal via an in-package clock distribution network from a clock source to clocked logic during normal operation. - View Dependent Claims (13, 14, 15, 16, 17)
-
-
18. A clock distribution system for a packaged semiconductor device, comprising:
-
means for transmitting a clock signal between a clock source and clocked logic on a chip via a chip conducting path present in the chip;
means for transmitting the clock signal between the clock source and the clocked logic via a package conducting path; and
means for providing the clock signal from the chip conducting path or the package conducting path to the clocked logic.
-
-
19. A computer system, comprising:
-
a packaged semiconductor device, including a clock distribution system comprising;
an on-chip clock distribution network for transmitting a clock signal between a clock source and clocked logic, an in-package clock distribution network for transmitting the clock signal between the clock source and the clocked logic, and a mode selector for providing the clock signal supplied by either the on-chip clock distribution network or the in-package clock distribution network to the clocked logic; and
a printed circuit board for supporting communications between the semiconductor device and other components of the computer system.
-
Specification