Method and apparatus to enforce clocked circuit functionality at reduced frequency without limiting peak performance
First Claim
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1. An apparatus for ensuring functionality of a clocked circuit without limiting peak performance, comprising:
- a de-skewing device, coupled to a data signal that is generated by a driver device at a time that is indicated by an assertion of a first clock signal, said de-skewing device for buffering said data signal in response to a de-assertion of a mode select signal and for gating said data signal in response to an assertion of said mode select signal until a second clock signal is asserted; and
a receiver device for receiving said data signal from said driver device via said de-skewing device, said receiver device latching said data signal in response to said assertion of said second clock signal, said receiver device being ensured of latching valid data from said data signal when said mode select signal is asserted, said mode select signal being asserted when a clock skew is detected between said first and second clock signals.
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Abstract
A method and apparatus are provided for ensuring that a clocked circuit will function after fabrication, regardless of the presence of clock skew. More particularly, a method and apparatus are shown for de-skewing the clock signals of such a clocked circuit only when clock skew is present. When such clock skew does not develop, peak performance of the associated circuit can be achieved by turning off the de-skewing function without removing that functionality from the circuit.
14 Citations
32 Claims
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1. An apparatus for ensuring functionality of a clocked circuit without limiting peak performance, comprising:
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a de-skewing device, coupled to a data signal that is generated by a driver device at a time that is indicated by an assertion of a first clock signal, said de-skewing device for buffering said data signal in response to a de-assertion of a mode select signal and for gating said data signal in response to an assertion of said mode select signal until a second clock signal is asserted; and
a receiver device for receiving said data signal from said driver device via said de-skewing device, said receiver device latching said data signal in response to said assertion of said second clock signal, said receiver device being ensured of latching valid data from said data signal when said mode select signal is asserted, said mode select signal being asserted when a clock skew is detected between said first and second clock signals. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
a first clock circuit for generating said first clock signal; and
a second clock circuit for generating said second clock signal, wherein said clock skew is a difference between when said first clock circuit asserts said first clock signal and when said second clock circuit asserts said second clock signal.
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3. The apparatus for ensuring functionality of said clocked circuit, as described in claim 2, wherein said driver device and said receiver device are edge triggered sense amplifiers.
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4. The apparatus for ensuring functionality of said clocked circuit, as described in claim 3, further comprising:
a logic circuit for performing a logic function between said second clock signal and said mode select signal such that said de-skew device performs a buffer operation when said mode select signal is de-asserted.
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5. The apparatus for ensuring functionality of said clocked circuit as described in claim 4 wherein the logic circuit is a logical-or circuit.
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6. The apparatus for ensuring functionality of said clocked circuit as described in claim 4 wherein the logic circuit is a logical-and circuit.
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7. The apparatus for ensuring functionality of said clocked circuit, as described in claim 4, wherein said de-skewing device performs a de-skewing operation when said mode select signal is asserted, said de-skewing operation being said gating of said data signal until said assertion of said second clock signal.
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8. The apparatus for ensuring functionality of said clocked circuit, as described in claim 7, wherein said mode select signal is de-asserted to allow said clocked circuit to operate at peak performance.
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9. The apparatus for ensuring functionality of said clocked circuit, as described in claim 8, wherein said de-skewing device and said logic circuit remain coupled to the clocked circuit in a production version of said clocked circuit without limiting peak performance of that clocked circuit.
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10. The apparatus for ensuring functionality of said clocked circuit, as described in claim 1, wherein a logic circuit performs a logic function on a data signal output from said de-skewing device before said data signal is conveyed to said receiver device.
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11. An apparatus for ensuring functionality of a clocked circuit without limiting peak performance, comprising:
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means for determining whether said clocked circuit will not function due to clock skew between a first clock signal clocking a first portion of said circuit and a second clock signal clocking a second portion of said circuit;
means for asserting a mode select signal in response to a determination that said clocked circuit will not function due to said clock skew;
means for performing a logic function on said second clock signal and said mode select signal to indicate an assertion of said second clock signal when said mode select signal is asserted; and
means for gating data, generated by said first portion of said clocked circuit, with an output of said logic function such that the said data remains stable until said output of said logic function indicates that said second clock signal has asserted. - View Dependent Claims (12, 13, 14, 15)
means for generating said first clock signal;
means for generating said second clock signal; and
means for de-asserting said mode select signal in response to a determination that said clock circuit is functional due to an absence of said clock skew such that said clocked circuit operates at peak performance.
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13. The apparatus for ensuring functionality of said clocked circuit, as described in claim 12, wherein said output of said logic function clocks a de-skewing unit that receives said data from said first portion of said clocked circuit and that outputs said data in response to said output of said logic function.
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14. The apparatus for ensuring functionality of said clocked circuit, as described in claim 13, wherein said de-skewing unit is an edge triggered sense amplifier.
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15. The apparatus for ensuring functionality of said clocked circuit, as described in claim 13, wherein said de-skewing unit is a flip-flop device.
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16. A computer system, comprising:
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a central processing unit coupled to a system bus;
a main memory coupled to said central processing unit by said system bus;
an I/O driver device coupled to said central processing unit by said system bus; and
a clocked circuit, included in said central processing unit, including a de-skewing device that can alternatively perform a de-skewing operation or a buffer operation such that said clocked circuit is ensured of being able to function in the presence of clock skew. - View Dependent Claims (17, 18, 19, 20, 21, 22, 23, 24, 25, 26)
a driver device, for generating a data signal at a time that is indicated by an assertion of a first clock signal;
said de-skewing device, coupled to said data signal, for immediately outputting said data signal in response to a de-assertion of a mode select signal and for outputting said data signal upon an assertion of a second clock signal in response to an assertion of said mode select signal;
a receiver device for receiving said data signal from said de-skewing device, said receiver device latching said data signal in response to said assertion of said second clock signal, said receiver device being ensured of latching valid data from said data signal when said mode select signal is asserted; and
said mode select signal being asserted when a clock skew is detected between said first and second clock signals.
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18. The computer system described in claim 17, wherein said clocked circuit further comprises:
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a first clock circuit for generating said first clock signal; and
a second clock circuit for generating said second clock signal, said clock skew being a difference between when said first clock circuit asserts said first clock signal and when said second clock circuit asserts said second clock signal.
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19. The computer system described in claim 17, wherein said driver device and said receiver device are edge triggered sense amplifiers.
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20. The computer system described in claim 17, wherein said clocked circuit further comprises:
a logic circuit for performing a logic function between said second clock signal and said mode select signal such that said de-skewing device performs a buffer operation when said mode select signal is de-asserted.
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21. The computer system described in claim 20 wherein the logic circuit is a logical-or circuit.
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22. The computer system described in claim 20 wherein the logic circuit is a logical-and circuit.
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23. The computer system described in claim 20, wherein said de-skewing device performs a de-skewing operation when said mode select signal is asserted, said de-skewing operation being said outputting of said data signal in response to said assertion of said mode select signal.
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24. The computer system described in claim 23, wherein said mode select signal is de-asserted to allow said clocked circuit to operate at peak performance.
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25. The computer system described in claim 24 wherein said de-skewing device and said logic circuit remain coupled to the clocked circuit in a production version of said clocked circuit without limiting peak performance of that clocked circuit.
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26. The computer system described in claim 25, wherein a logic circuit performs a logic function on a data signal output from said de-skewing device before said data signal is conveyed to said receiver device.
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27. A method for ensuring functionality of a clocked circuit without limiting peak performance, comprising the steps of:
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determining whether said clocked circuit will not function due to clock skew between a first clock signal clocking a first portion of said circuit and a second clock signal clocking a second portion of said circuit;
asserting a mode select signal in response to a determination that said clocked circuit will not function due to said clock skew;
performing a logic function on said second clock signal and said mode select signal to indicate an assertion of said second clock signal when said mode select signal is asserted;
gating data generated by said first portion of said clocked circuit with an output of said logic function such that said data remains stable until said output of said logic function indicates that said second clock signal has asserted;
de-asserting said mode select signal in response to a determination that said clock skew is not present in said clocked circuit; and
buffering data, generated by a driver portion of said clocked signal, in response to said de-assertion of said mode select signal. - View Dependent Claims (28, 29, 30, 31, 32)
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Specification