Semiconductor device including macros and its testing method
First Claim
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1. A semiconductor device comprising:
- a common bus;
a first macro having an output terminal, said first macro including a first internal circuit having an output node coupled to said output terminal and a register coupled between said output terminal and said common bus, said register storing a test data supplied from said common bus;
a second macro having an input terminal, said second macro including a second internal circuit having an input node coupled to said input terminal and a buffer coupled between said input terminal and said common bus, said buffer supplying a data of said input terminal to said common bus; and
a connection connected between said output terminal and said input terminal.
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Abstract
A semiconductor device includes a common bus and a plurality of macros connected in series by connections. Each of the macros is constructed by an internal circuit, a buffer connected between an input of the internal circuit and the common bus, a register connected to the common bus, and a logic circuit for selecting one of an output signal of the internal circuit and an output signal of the register.
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Citations
9 Claims
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1. A semiconductor device comprising:
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a common bus;
a first macro having an output terminal, said first macro including a first internal circuit having an output node coupled to said output terminal and a register coupled between said output terminal and said common bus, said register storing a test data supplied from said common bus;
a second macro having an input terminal, said second macro including a second internal circuit having an input node coupled to said input terminal and a buffer coupled between said input terminal and said common bus, said buffer supplying a data of said input terminal to said common bus; and
a connection connected between said output terminal and said input terminal. - View Dependent Claims (2, 3)
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4. A semiconductor device comprising:
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a common bus;
a first macro having an output terminal, said first macro including a first internal circuit having an output node, a register coupled to said common bus, and a gate circuit connected among said output node, said register and said output terminal;
a second macro having an input terminal, said second macro including a second internal circuit having an input node coupled to said input terminal and a buffer coupled to said input terminal and said common bus; and
a connection connected between said output terminal and said input terminal. - View Dependent Claims (5, 6)
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7. A semiconductor device comprising:
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a common bus;
a first macro having an output terminal, said first macro including a first internal circuit having an output node coupled to including a first internal circuit having an output node coupled to said output terminal and a register coupled between said output terminal and said common bus;
a second macro having an input terminal, said second macro including a second internal circuit having an input node coupled to said input terminal, a selector coupled among said input terminal, said input node, and a test input terminal, and a buffer coupled between said common bus; and
a connection connected between said output terminal and said input terminal. - View Dependent Claims (8, 9)
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Specification