Semiconductor device including macros and its testing method

• US 6,463,562 B1
• Filed: 06/01/2000
• Issued: 10/08/2002
• Est. Priority Date: 06/04/1999
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Corporation
• Inventors: Otsuka, Shigekazu
• Primary Examiner(s): Decady, Albert
• Assistant Examiner(s): Amanze, Emeka J.
• Application Number:
  US09/585,836
• Time in Patent Office: 859 Days
• Field of Search: 714/736, 714/737, 714/724, 324/73, 324/16, 324/487, 324/492
• US Class Current: 714/742
• CPC Class Codes: G01R 31/318505 Test of Modular systems, e.g. Wafers, MCM's
• CPC Class Codes: G01R 31/318536 Scan chain arrangements, e.g. connections, test bus, analog signals

Abstract

A semiconductor device includes a common bus and a plurality of macros connected in series by connections. Each of the macros is constructed by an internal circuit, a buffer connected between an input of the internal circuit and the common bus, a register connected to the common bus, and a logic circuit for selecting one of an output signal of the internal circuit and an output signal of the register.

Claims

1. A semiconductor device comprising:

a common bus;

a first macro having an output terminal, said first macro including a first internal circuit having an output node coupled to said output terminal and a register coupled between said output terminal and said common bus, said register storing a test data supplied from said common bus;

a second macro having an input terminal, said second macro including a second internal circuit having an input node coupled to said input terminal and a buffer coupled between said input terminal and said common bus, said buffer supplying a data of said input terminal to said common bus; and

a connection connected between said output terminal and said input terminal.

2. The device as claimed in claim 1, further comprising a selector coupled among an input terminal of said first macro, an input node of said first internal circuit, and a test input terminal.

3. The device as claimed in claim 1, further comprising a test output terminal coupled to said output terminal.

4. A semiconductor device comprising:

a common bus;

a first macro having an output terminal, said first macro including a first internal circuit having an output node, a register coupled to said common bus, and a gate circuit connected among said output node, said register and said output terminal;

a second macro having an input terminal, said second macro including a second internal circuit having an input node coupled to said input terminal and a buffer coupled to said input terminal and said common bus; and

a connection connected between said output terminal and said input terminal.

5. The device as claimed in claim 4, further comprising a selector coupled among an input terminal of said first macro, an input node of said first internal circuit and a test input terminal.

6. The device as claimed in claim 4, further comprising a test output terminal coupled to said output terminal.

7. A semiconductor device comprising:

a common bus;

a first macro having an output terminal, said first macro including a first internal circuit having an output node coupled to including a first internal circuit having an output node coupled to said output terminal and a register coupled between said output terminal and said common bus;

a second macro having an input terminal, said second macro including a second internal circuit having an input node coupled to said input terminal, a selector coupled among said input terminal, said input node, and a test input terminal, and a buffer coupled between said common bus; and

a connection connected between said output terminal and said input terminal.

8. The device as claimed in claim 7, further comprising a selector coupled among an input terminal of said first macro, an input node of said first internal circuit, and a test input terminal.

9. The device as claimed in claim 7, further comprising a test output terminal coupled to said output terminal.