Method of fabricating silicon capacitive sensor

• US 6,465,271 B1
• Filed: 01/05/2001
• Issued: 10/15/2002
• Est. Priority Date: 07/07/1998
• Status: Expired due to Fees

• Current Assignee: Case Western Reserve University
• Original Assignee: Qiang Wang, Wen H. Ko
• Inventors: Wang, Qiang, Ko, Wen H.
• Primary Examiner(s): Mulpuri, Savitri
• Application Number:
  US09/743,432
• Time in Patent Office: 648 Days
• Field of Search: 737/18, 737/24, 737/54, 361/283.4, 361/283.1, 438/48, 438/50, 438/53, 438/455, 438/456, 438/459, 438/462, 438/460, 438/977
• US Class Current: 438/48
• CPC Class Codes: G01D 5/2417 by varying separation
• CPC Class Codes: G01L 17/00 Devices or apparatus for measuring tyre pressure or the pressure in other inflated bodies
• CPC Class Codes: G01L 9/0042 Constructional details associated with semiconductive diaphragm sensors, e.g. etching, or constructional details of non-semiconductive diaphragms details about the integration or bonding of piezoresistor in or on the diaphragm G01L9/0052 and G01L9/0057 respectively
• CPC Class Codes: G01L 9/0073 using a semiconductive diaphragm
• CPC Class Codes: G01L 9/125 with temperature compensating means non electric temperature compensating means G01L19/04

Abstract

Manufacturing all-silicon force sensors, such as capacitive pressure sensors (100, 200) that have long term stability and good linear sensitivity, and can be built into of a pneumatic tire. The sensors include buried electrical feedthrough (112b) to provide an electrical connection into a sealed silicon cavity (108). The buried feedthrough consists of a conductor (112b) in a shallow groove (106) in a substrate (102), communicating between the sensing cavity (108) and an external contact area (110). The sensor designs also feature a method for forming a silicon-to-silicon fusion bond (SFB) wherein at least one of the two surfaces (152, 252) to be has a tough silicon surface unsuitable for good SFB joints because it was bonded heavily boron-doped by means of diffusion. The method of this invention includes preparing each doped surface (152, 252) for SFB by polishing the surface with a Chemical-Mechanical Polishing (CMP) process. The sensor designs can also include optional reference capacitors (141, 241) on the same chip (100, 200) as the sensing capacitor (140, 240). The reference capacitors (141, 241) are insensitive to pressure (force), but respond to ambient temperature changes in the same way as the sensing capacitor. Suitable external interface circuits can utilize the reference capacitors (141, 241) to pull out the majority of ambient temperature effects.

Claims

1. A method of fabricating silicon capacitive sensors, characterized by the steps of:

providing a first silicon wafer and a second silicon wafer;

for each sensor, etching a groove in the first silicon wafer;

for each sensor, etching a sensing cavity and a contact cavity, each cavity connected to an opposing end of the groove in the first silicon wafer;

for each sensor, after etching the groove and the cavities, forming a continuous and connected conductive area in the bottoms of the groove and the cavities, in the first silicon wafer;

forming a P+ conductive diaphragm layer in the second silicon wafer by means of diffusion doping;

after the step of forming the diaphragm layer in the second silicon wafer, preparing the surface of the diaphragm layer for bonding by polishing with a chemical-mechanical polishing (CMP) process;

bonding the first silicon wafer and the second silicon wafer together using a silicon fusion bonding (SFB) technique;

dissolving the second silicon wafer, except for the diaphragm layer;

after the step of dissolving the second silicon wafer, for each sensor, etching open a fixed electrode contact window through the diaphragm layer to the contact cavity; and

dicing a plurality of sensors formed from the first and second silicon wafers.

2. Method, according to claim 1, including the steps of:

providing the first silicon wafer as an N-type silicon wafer, <

100>

orientation, with resistivity of 5-10 ohm-cm; and

providing the second silicon wafer as a P-type silicon wafer, <

100>

orientation, with resistivity of 2-5 ohm-cm.

3. Method, according to claim 1, including the steps of:

for each sensor, after forming a conductive area in the bottom of the sensing cavity, forming an oxide layer over the conductive area in the bottom of the sensing cavity, in the first silicon wafer; and

after forming a conductive area in the bottom of the groove which connects to the sensing cavity conductive area, forming an oxide layer over the conductive area in the bottom of the groove (106) and extending into the sensing cavity, in the first silicon wafer.

4. Method, according to claim 1, including the steps of:

sealing the grooves by depositing a layer of LTO; and

masking and etching the LTO layer to open windows through the LTO layer including a diaphragm window, a fixed electrode contact window, a diaphragm contact window, and a window above a reference capacitor contact, if present.

5. Method, according to claim 1, including the step of:

for each sensing capacitor in each sensor, fabricating an associated reference capacitor with a reference capacitor bottom electrode, a reference capacitor bottom electrode contact, a reference capacitor feedthrough which electrically connects the reference capacitor bottom electrode to the reference capacitor bottom electrode contact, a reference capacitor contact pad, a dielectric oxide layer, and a top electrode which is the diaphragm layer.

6. Method, according to claim 1, for each sensor, after the step of etching open a window through the diaphragm layer to the fixed electrode contact cavity, further including the steps of:

depositing metallization on the fixed electrode contact to form a sensing capacitor fixed electrode contact pad; and

depositing metallization on the diaphragm layer to form a diaphragm contact pad.

7. Method, according to claim 1, including the step of:

during the step of etching the cavities, over-etch to create a step around the periphery of the cavities.

8. Method, according to claim 1, including the step of:

during the step of etching the cavities, round off edges of the cavities.

9. Method, according to claim 1, wherein the step of forming the conductive area for each sensor further includes the steps of:

applying and patterning a masking layer; and

heavily diffusing boron (+).

10. Method, according to claim 1, further including the step of:

prior to silicon fusion bonding the wafers, preparing the wafers for silicon fusion bonding by RCA cleaning.

11. Method, according to claim 1, including the step of dissolving the second silicon wafer by:

dissolving in EDP.

12. A silicon capacitive sensor including a first silicon wafer and a second silicon wafer, characterized by:

a groove etched in the first silicon wafer;

a sensing cavity and a contact cavity etched in the first silicon wafer with each cavity connected to an opposing end of the groove;

a continuous and connected conductive area in the bottoms of the groove and the cavities, in the first silicon wafer;

a P+ conductive diaphragm layer formed in the second silicon wafer;

the first and second wafers being bonded together, with the second silicon wafer being dissolved except for the diaphragm layer; and

a window through the diaphragm layer to the contact cavity.

13. A silicon capacitive sensor, according to claim 12, characterized in that:

the first silicon wafer is an N-type silicon wafer with resistivity of 5-10 ohm-cm; and

the second silicon wafer is a P-type silicon wafer with resistivity of 2-5 ohm-cm.

14. A silicon capacitive sensor, according to claim 12, characterized in that:

an oxide layer is over the conductive area in the bottom of the sensing cavity; and

an oxide layer is over the conductive area in the bottom of the groove and extends into the sensing cavity.

15. A silicon capacitive sensor, according to claim 12, characterized in that:

the grooves are sealed by a deposited layer of LTO; and

windows pass through the LTO layer to form a diaphragm window, a fixed electrode contact window, a diaphragm contact window, and a window above a reference capacitor contact.

16. A silicon capacitive sensor, according to claim 12, further characterized by:

a sensing capacitor; and

an associated reference capacitor with a reference capacitor bottom electrode, a reference capacitor bottom electrode contact, a reference capacitor feedthrough which electrically connects the reference capacitor bottom electrode to the reference capacitor bottom electrode contact, a reference capacitor contact pad, a dielectric oxide layer, and a top electrode being the diaphragm layer.

17. A silicon capacitive sensor, according to claim 12, characterized in that:

deposited metallization on the fixed electrode contact forms a sensing capacitor fixed electrode contact pad; and

deposited metallization on the diaphragm layer forms a diaphragm contact pad.

18. A method for forming an electrical feedthrough to a conductor in a cavity formed in a first silicon wafer, wherein the first silicon wafer is bonded to a second silicon wafer, characterized by the steps of:

etching a groove in the first silicon wafer;

etching the cavity and a contact cavity, each cavity connected to an opposing end of the groove in the first silicon wafer;

forming a continuous and connected conductive area in the bottoms of the groove and the cavities, in the first silicon wafer;

bonding the first and second wafers together using silicon fusion bonding (SFB);

etching a window through the second wafer to the contact cavity on the first silicon wafer;

forming an oxide layer over the conductive area in the bottom of the sensing cavity, in the first silicon wafer; and

forming an oxide layer over the conductive area in the bottom of the groove and extending into the cavity, in the first silicon wafer.

19. A method for forming an electrical feedthrough to a conductor in a cavity formed in a first silicon wafer, wherein the first silicon wafer is bonded to a second silicon wafer, characterized by the steps of:

etching a groove in the first silicon wafer;

etching the cavity and a contact cavity, each cavity connected to an opposing end of the groove in the first silicon wafer;

forming a continuous and connected conductive area in the bottoms of the groove and the cavities, in the first silicon wafer;

bonding the first and second wafers together using silicon fusion bonding (SFB);

etching a window through the second wafer to the contact cavity on the first silicon wafer

sealing the groove by depositing LTO; and

opening a window above a contact portion of the conductive area, by etching the LTO.