Structure and fabrication method using latch-up implantation for improving latch-up immunity in CMOS fabrication process

• US 6,465,283 B1
• Filed: 09/05/2000
• Issued: 10/15/2002
• Est. Priority Date: 02/01/2000
• Status: Expired due to Term

• Current Assignee: Transpacific IP Group Limited
• Original Assignee: Industrial Technology Research Institute
• Inventors: Chang, Chyh-Yih, Peng, Jeng-Jie, Ker, Ming-Dou, Jiang, Hsin-Chin
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): MALSAWMA, LALRINFAMKIM HMAR
• Application Number:
  US09/654,810
• Time in Patent Office: 770 Days
• Field of Search: 257/133, 257/139, 257/142, 257/168, 257/170, 257/369, 257/372, 438/133, 438/135, 438/140, 438/199
• US Class Current: 438/135
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/0921 Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention

Abstract

A structure and fabrication method using latch-up implantation to improve latch-up immunity in CMOS circuit. The impedance of parasitic SCR conducting path is raised by performing an ion-implantation process on a cathode and an anode of a parasitic SCR which may induce latch-up phenomenon. Thus, the parasitic SCR is thus not easily to be conducted with a higher resistance to noise. Therefore, the latch-up immunity can be improved. In addition, the ion implantation process can be performed to achieve the objective of preventing latch-up effect without consuming more area for layout, thus greatly enhances the flexibility in circuit design.

Claims

1. A structure using latch-up implantation to improve latch-up immunity in CMOS fabrication process, the structure comprising:

a substrate, having a first conductive type;

a well, formed in the substrate and having a second conductive type;

a first MOS transistor formed in the second conductive type well, having a first source and a first drain regions with a first conductive type and a gate;

a second MOS transistor formed in the first conductive type substrate, having a second source and a second drain regions with a second conductive type and a gate;

a first lightly doped region surrounding a bottom and edges of the first source region in the well, the edges of the first source region excluding the edge at a near side of the first drain region, and the first lightly doped region having a first conductive type;

a second lightly doped region surrounding a bottom and edges of the second source region in the substrate, the edges of the second source region excluding the edge at a near side of the second drain region, and the second lightly doped region having a second conductive type;

a first heavily doped region with a second conductive type in the second conductive type well, the first heavily doped region being near and with a distance to the first lightly doped region; and

a second heavily doped region with a first conductive type in the first conductive type substrate, the second heavily doped region being near and with a distance to the second lightly doped region.

2. The structure according to claim 1, wherein the first conductive type includes P-type and the second conductive type includes N-type.

3. The structure according to claim 1, wherein the first conductive type includes N-type and the second conductive type includes P-type.

4. A structure using latch-up implantation to improve latch-up immunity in CMOS fabrication process, the structure comprising:

a substrate, having a first conductive type;

a well, formed in the substrate and having a second conductive type;

a first MOS transistor formed in the second conductive type well, having a first source and a first drain regions with a first conductive type and a gate;

a second MOS transistor formed in the first conductive type substrate, having a second source and a second drain regions with a second conductive type and a gate;

a first lightly doped region surrounding a bottom and edges of the first source region in the well, the edges of the first source region excluding the edge at a near side of the first drain region, and the first lightly doped region having a first conductive type;

a first heavily doped region with a second conductive type in the second conductive type well, the first heavily doped region being near and with a distance to the first lightly doped region; and

a second heavily doped region with a first conductive type in the first conductive type substrate, the second heavily doped region being near and with a distance to a second lightly doped region, wherein the second lightly doped region is located in the first conductive type substrate.

5. The structure according to claim 4, wherein the first conductive type includes P-type and the second conductive type includes N-type.

6. The structure according to claim 4, wherein the first conductive type includes N-type and the second conductive type includes P-type.

7. A structure using latch-up implantation to improve latch-up immunity in CMOS fabrication process, the structure comprising:

a substrate, having a first conductive type;

a well, formed in the substrate and having a second conductive type;

a first MOS transistor formed in the second conductive type well, having a first source and a first drain regions with a first conductive type and a gate;

a second MOS transistor formed in the first conductive type substrate, having a second source and a second drain regions with a second conductive type and a gate;

a first lightly doped region surrounding a bottom and edges of the second source region in the substrate, the edges of the second source region excluding the edge at a near side of the second drain region, and the first lightly doped region having a second conductive type;

a first heavily doped region with a second conductive type in the second conductive type well, the first heavily doped region being near and with a distance to the first lightly doped region; and

a second heavily doped region with a first conductive type in the first conductive type substrate, the second heavily doped region being near and with a distance to a second lightly doped region, wherein the second lightly doped region is located in the first conductive type substrate.

8. The structure according to claim 7, wherein the first conductive type includes P-type and the second conductive type includes N-type.

9. The structure according to claim 7, wherein the first conductive type includes N-type and the second conductive type includes P-type.

10. A method using latch-up implantation to improve latch-up immunity in CMOS fabrication process, the method comprising:

providing a first conductive type substrate comprising a second conductive type well thereon;

forming a first MOS in the second conductive type well and a first heavily doped region with a first conductive type in the first conductive type substrate;

forming a second MOS in the first conductive type substrate and a second heavily doped region with a second conductive type in the second conductive type well;

forming a first lightly doped region with a first conductive type surrounding a bottom and edges of a source region of the first MOS in the well, wherein the edges are those edges except the edge being at near to the drain region of the first MOS; and

forming a second lightly doped region with a second conductive type surrounding a bottom and edges of a source region of the second MOS in the substrate, wherein the edges are those edges except the edge being at near to the drain region of the second MOS.

11. The method of claim 10, wherein the first and the second lightly doped regions are formed out of the channel regions of the first and the second MOS'"'"'s, respectively.

12. The method of claim 10, wherein the step of forming the first MOS includes forming a PMOS, the first conductive type includes P-type, the step of forming the second MOS includes forming a NMOS, and the second conductive type includes N-type.

13. The method of claim 10, wherein the step of forming the first MOS includes forming a NMOS, the first conductive type includes N-type, the step of forming the second MOS includes forming a PMOS, and the second conductive type includes P-type.

14. A method using latch-up implantation to improve latch-up immunity in CMOS fabrication process, the method comprising:

providing a first conductive type substrate comprising a second conductive type well thereon;

forming a first MOS in the second conductive type well and a first heavily doped region with a first conductive type in the first conductive type substrate;

forming a second MOS in the first conductive type substrate and a second heavily doped region with a second conductive type in the second conductive type well;

forming a first lightly doped region with a first conductive type surrounding a bottom and edges of a source region of the first MOS in the well, wherein the edges are those edges except the edge being at near to the drain region of the first MOS.

15. The method of claim 14, wherein the first lightly doped region is formed out of the channel regions of the first MOS.

16. The method of claim 14, wherein the step of forming the first MOS includes forming a PMOS, the first conductive type includes P-type, the step of forming the second MOS includes forming a NMOS, and the second conductive type includes N-type.

17. The method of claim 14, wherein the step of forming the first MOS includes forming a NMOS, the first conductive type includes N-type, the step of forming the second MOS includes forming a PMOS, and the second conductive type includes P-type.

18. A method using latch-up implantation to improve latch-up immunity in CMOS fabrication process, the method comprising:

providing a first conductive type substrate comprising a second conductive type well thereon;

forming a first MOS in the second conductive type well and a first heavily doped region with a first conductive type in the first conductive type substrate;

forming a second MOS in the first conductive type substrate and a second heavily doped region with a second conductive type in the second conductive type well;

forming a first lightly doped region with a second conductive type surrounding a bottom and edges of a source region of the second MOS in the substrate, wherein the edges are those edges except the edge being at near to the drain region of the second MOS.

19. The method of claim 18, wherein the first lightly doped region is formed out of the channel regions of the second MOS.

20. The method of claim 18, wherein the step of forming the first MOS includes forming a PMOS, the first conductive type includes P-type, the step of forming the second MOS includes forming a NMOS, and the second conductive type includes N-type.

21. The method of claim 18, wherein the step of forming the first MOS includes forming a NMOS, the first conductive type includes N-type, the step of forming the second MOS includes forming a PMOS, and the second conductive type includes P-type.