Method of fabricating a semiconductor-on-insulator memory cell with buried word and body lines

• US 6,465,298 B2
• Filed: 02/22/2000
• Issued: 10/15/2002
• Est. Priority Date: 07/08/1997
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Ahn, Kie Y., Forbes, Leonard
• Primary Examiner(s): Nguyen, Tuan H.
• Application Number:
  US09/510,095
• Publication Number:
  US 20010053577A1
• Time in Patent Office: 966 Days
• Field of Search: 438/243, 438/151, 438/156, 438/244, 438/268, 438/270, 438/242
• US Class Current: 438/242
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 12/31 having a storage electrode stacked over the transistor
• CPC Class Codes: H10B 12/482 Bit lines
• CPC Class Codes: H10B 12/488 Word lines

Abstract

A memory cell array for a dynamic random access memory (DRAM) includes word and body lines that are buried below the active semiconductor surface in dielectric material in alternating parallel isolation trenches between adjacent ones of the memory cells. Semiconductor-on-insulator (SOI) processing techniques form the access transistor of each memory cell on a silicon island defined by the trenches and isolated from the substrate by an insulating layer. The word and body lines are oriented in the trenches to have a line width that is less than a minimum lithographic feature size F. The memory cells, including portions of the word and body lines, have a surface area of about 8 F². Also disclosed is a process for fabricating the DRAM cell using SOI processing techniques.

Claims

1. A method of fabricating a memory array on a semiconductor substrate, comprising:

defining a bar of semiconductor material in the substrate;

forming an insulating layer between the bar and the substrate for providing electrical isolation therebetween;

defining a plurality of active areas of semiconductor material on the bar;

producing an access transistor in each of the active areas, each access transistor including gate, body, and first and second source/drain regions;

forming a word line trench and a word line in the word line trench;

coupling the word line to the gate region of at least one of the access transistors;

forming a body line trench and a body line in the body line trench; and

electrically connecting the body line to the body region of at least one of the access transistors.

2. The method of claim 1, wherein forming the insulating layer between the bar and the substrate includes partially undercutting the bar using an isotropic etch and oxidizing to fully isolate the bottom of the bar from the substrate.

3. The method of claim 1, wherein defining the active areas includes forming oxide between portions of the semiconductor material that forms the bar.

4. The method of claim 1, including forming the word and body lines prior to producing the access transistors.

5. The method of claim 1, including producing the access transistors prior to forming the word and body lines.

6. The method of claim 1, including forming the word line and the body contact line to be located at a height that is no higher than an upper surface of the access transistors.

7. The method of claim 1, including electrically coupling the word line to the gate regions of a plurality of the access transistors, and electrically coupling the body line to the body regions of a plurality of the access transistors.

8. The method of claim 1, including:

interposing an insulating layer between the body line and the second trench;

forming a plurality of contact openings through the insulating layer between the body line and the body regions of the access transistors; and

forming contacts in the contact openings for electrically coupling the body line and the body regions of the access transistors.

9. The method of claim 8, wherein forming the contact openings includes:

defining, by photoresist, regions in the insulating layer in the second trench in which the contact openings are to be formed; and

etching the contact openings using a reactive ion etch (RIE) process.

10. The method of claim 9, further including overexposing the photoresist material and over etching the contact openings to define oversized contact openings.

11. A method for fabricating a memory array on a semiconductor substrate, comprising:

defining at least first, second and third bars of semiconductor material in the substrate;

forming an insulating layer between the bars and the substrate for providing electrical isolation therebetween;

defining a plurality of semiconductor active areas on each of the bars;

producing an access transistor in each of the active areas, each access transistor including gate, body, and first and second source/drain regions;

forming a first word line trench and a word line in the first word line trench;

coupling the word line to the gate region of a plurality of the access transistors on the first and second bars;

forming a first body line trench and a body line in the first body line trench; and

electrically coupling the body line to the body region of a plurality of the access transistors on the second and third bars.

12. A method of fabricating a memory array on a semiconductor substrate, comprising:

forming at least first and second trenches in the substrate to define a bar of semiconductor material;

forming an insulating layer between the bar and the substrate for providing electrical isolation therebetween, including;

partially undercutting the bar using an isotropic etch; and

oxidizing to fully isolate the bottom of the bar from the substrate;

defining a plurality of active areas of semiconductor material on the bar, including forming oxide between portions of the semiconductor material that forms the bar;

producing an access transistor in each of the active areas, each access transistor including gate, body, and first and second source/drain regions;

forming a buried word line;

coupling the word line to the gate region of at least one of the access transistors;

forming a buried body line; and

electrically connecting the body line to the body region of at least one of the access transistors.

13. The method of claim 12, wherein forming a buried word line and forming a buried body line are performed prior to producing an access transistor.

14. The method of claim 12, wherein producing an access transistor is performed prior to forming a buried word line and forming a buried body line.

15. The method of claim 12, further including fabricating a storage capacitor over each of the active areas, wherein the capacitor is operably connected to the access transistor.

16. A method of fabricating a memory array on a semiconductor substrate, comprising:

forming at least first and second trenches in the substrate to define a bar of semiconductor material;

forming an insulating layer between the bar and the substrate for providing electrical isolation therebetween;

defining a plurality of active areas of semiconductor material on the bar;

producing an access transistor in each of the active areas, each access transistor including gate, body, and first and second source/drain regions, each access transistor having an upper surface;

forming a buried word line at a height that is no higher than the upper surface of the access transistors;

forming a buried body line at a height that is no higher than the upper surface of the access transistors;

electrically coupling the buried word line to the gate regions of a plurality of the access transistors; and

electrically coupling the buried body line to the body regions of a plurality of the access transistors.

17. The method of claim 16, wherein forming a buried word line and forming a buried body line are performed prior to producing an access transistor.

18. The method of claim 16, wherein producing an access transistor is performed prior to forming a buried word line and forming a buried body line.

19. The method of claim 16, further including fabricating a storage capacitor over each of the active areas, wherein the capacitor is operably connected to the access transistor.

20. A method of fabricating a memory array on a semiconductor substrate, comprising:

forming at least first and second trenches in the substrate to define a bar of semiconductor material;

forming an insulating layer between the bar and the substrate for providing electrical isolation therebetween;

defining a plurality of active areas of semiconductor material on the bar;

producing an access transistor in each of the active areas, each access transistor including gate, body, and first and second source/drain regions;

forming a buried word line;

coupling the word line to the gate region of at least one of the access transistors;

forming a buried body line;

electrically connecting the body line to the body region of at least one of the access transistors;

forming a plurality of contact openings through an insulating layer between the buried body line and the body regions of the access transistors; and

forming contacts in the contact openings for electrically coupling the buried body line and the body regions of the access transistors.

21. The method of claim 20, wherein forming a buried word line and forming a buried body line are performed prior to producing an access transistor.

22. The method of claim 20, wherein producing an access transistor is performed prior to forming a buried word line and forming a buried body line.

23. The method of claim 20, wherein forming the contact openings includes:

defining regions in the insulating layer in the second trench in which the contact openings are to be formed; and

etching the contact openings using a reactive ion etch (RIE) process.

24. The method of claim 23, further including overexposing a photoresist material and over etching the contact openings to define oversized contact openings.

25. The method of claim 20, further including fabricating a storage capacitor over each of the active areas, wherein the capacitor is operably connected to the access transistor.

26. A method for fabricating a memory array, comprising:

isolating a row of semiconductor material from a substrate;

defining a plurality of islands in the row;

forming a transistor on each of the islands, wherein each transistor includes a gate region, a body region, and two source/drain regions;

forming a body line trench and a body line in each body line trench, wherein the body line is in electrical contact with the body regions through a body contact opening extending from the body line trench to the body regions of the transistors;

forming a word line trench and a word line in each word line trench, wherein the word line is in electrical contract with the gate regions of the transistors;

forming bit lines to contact one of the source/drain regions of the transistors; and

forming a capacitor over the islands, wherein the capacitor is electrically connected to the other one of the source/drain regions of the transistors.

27. The method of claim 26, wherein isolating the row from the substrate comprises:

undercutting the row using an etching process; and

oxidizing the substrate to isolate the rows from the substrate.

28. The method of claim 26, wherein isolating the row from the substrate further comprises:

forming a cap on the row;

undercutting the row using an etching process; and

providing an oxide between the row and the substrate.

29. The method of claim 28, wherein undercutting the row includes partially undercutting the row using an etching process.

30. The method of claim 28, wherein providing an oxide between the row and the substrate includes oxidizing the substrate.

31. The method of claim 26, wherein defining a plurality of islands in the row comprises forming oxide areas between active areas of islands.

32. A method for fabricating a memory array, comprising:

forming at least one row of active islands insulated from an underlying semiconductor substrate using a semiconductor-on-insulator technique;

forming a transistor on each of at least one of the active islands;

forming a body line trench on a first side of the at least one row of active islands;

forming a word line trench on a second side of the at least one row of active islands;

forming a body line in the body line trench;

forming a word line in the word line trench; and

operably connecting the body line and the word line to the transistor.

33. The method of claim 32, wherein forming a word line and forming a body line are performed prior to forming a transistor.

34. The method of claim 32, wherein forming a transistor is performed prior to forming a word line and forming a body line.

35. The method of claim 32, further comprising:

forming a bit line operably connected to the transistor; and

forming a capacitor over the active island, wherein the capacitor is operably connected to the transistor.